linux-kernel - Re: [PATCH v2 4/4] crypto: s5p-sss: Add aes-ctr support

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Message-Id: <20180917155422eucas1p2ea33c73f046cb19c7be5fac7e9191059~VOvLUVLIR0418604186eucas1p2i@eucas1p2.samsung.com>
Date:   Mon, 17 Sep 2018 17:54:20 +0200
From:   Kamil Konieczny <k.konieczny@...tner.samsung.com>
To:     Christoph Manszewski <c.manszewski@...sung.com>,
        linux-crypto@...r.kernel.org
Cc:     Krzysztof Kozlowski <krzk@...nel.org>,
        Vladimir Zapolskiy <vz@...ia.com>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        "David S. Miller" <davem@...emloft.net>,
        linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
Subject: Re: [PATCH v2 4/4] crypto: s5p-sss: Add aes-ctr support



On 17.09.2018 17:09, Christoph Manszewski wrote:
> Add support for aes counter(ctr) block cipher mode of operation for
> Exynos Hardware. In contrast to ecb and cbc modes, aes-ctr allows
> encyption/decryption for request sizes not being a multiple of 16(bytes).
> 
> Hardware requires block sizes being a multiple of 16(bytes). In order to
> achieve this, copy request source and destination memory, and align it's size
> to 16. That way hardware processes additional bytes, that are omitted
> when copying the result back to its original destination.
> 
> Tested on Odroid-U3 with Exynos 4412 CPU, kernel 4.19-rc2 with crypto
> run-time self test testmgr.
> 
> Signed-off-by: Christoph Manszewski <c.manszewski@...sung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org>
> ---
>  drivers/crypto/s5p-sss.c | 45 ++++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index ba8f2e2ea88f..0064be0e3941 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -1813,7 +1813,7 @@ static struct ahash_alg algs_sha1_md5_sha256[] = {
>  };
>  
>  static void s5p_set_aes(struct s5p_aes_dev *dev,
> -			const u8 *key, const u8 *iv,
> +			const u8 *key, const u8 *iv, const u8 *ctr,
>  			unsigned int keylen)
>  {
>  	void __iomem *keystart;
> @@ -1821,6 +1821,9 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
>  	if (iv)
>  		memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
>  
> +	if (ctr)
> +		memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, 0x10);
> +
>  	if (keylen == AES_KEYSIZE_256)
>  		keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
>  	else if (keylen == AES_KEYSIZE_192)
> @@ -1902,8 +1905,9 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
>  	u32 aes_control;
>  	unsigned long flags;
>  	int err;
> -	u8 *iv;
> +	u8 *iv, *ctr;
>  
> +	/* This sets bit [13:12] to 00, which selects 128-bit counter */

s/bit/bits/

This this,

Acked-by: Kamil Konieczny <k.konieczny@...tner.samsung.com>

Thanks!
Kamil