[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAAhSdy3NSNn=YicWdnyos87A7gDq0O1BMvQQ0FVmCtv+rBo=vg@mail.gmail.com>
Date: Mon, 17 Sep 2018 21:24:31 +0530
From: Anup Patel <anup@...infault.org>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Christoph Hellwig <hch@...radead.org>,
Atish Patra <atish.patra@....com>,
Palmer Dabbelt <palmer@...ive.com>,
linux-riscv@...ts.infradead.org,
Mark Rutland <mark.rutland@....com>, robh@...nel.org,
Damien Le Moal <Damien.LeMoal@....com>,
Marc Zyngier <marc.zyngier@....com>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC 3/3] RISC-V: Remove per cpu clocksource
On Mon, Sep 17, 2018 at 8:35 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
> On Mon, 17 Sep 2018, Christoph Hellwig wrote:
> > > Just for the record, this would be the first (architected) timer ever which
> > > just works. I'm having a hard time to believe this, but I'd certainly
> > > welcome it.
> >
> > And that would be the contact with reality.
>
> I've dealt with the reality of timers for a long time ....
I think the problem is we don't have separate DT node
for RISC-V timer. Instead, we have been probing timer
for each CPU DT node.
Ideally, we should have one DT node for RISC-V timer
and the DT should should also describe the local interrupts
to be used for RISC-V timer.
Regards,
Anup
Powered by blists - more mailing lists