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Message-ID: <20180924185753.GA32269@bombadil.infradead.org>
Date: Mon, 24 Sep 2018 11:57:53 -0700
From: Matthew Wilcox <willy@...radead.org>
To: Bart Van Assche <bvanassche@....org>
Cc: Andrey Ryabinin <aryabinin@...tuozzo.com>,
Ming Lei <ming.lei@...hat.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Christoph Hellwig <hch@....de>,
Ming Lei <tom.leiming@...il.com>,
linux-block <linux-block@...r.kernel.org>,
linux-mm <linux-mm@...ck.org>,
Linux FS Devel <linux-fsdevel@...r.kernel.org>,
"open list:XFS FILESYSTEM" <linux-xfs@...r.kernel.org>,
Dave Chinner <dchinner@...hat.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Jens Axboe <axboe@...nel.dk>, Christoph Lameter <cl@...ux.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Subject: Re: block: DMA alignment of IO buffer allocated from slab
On Mon, Sep 24, 2018 at 09:19:44AM -0700, Bart Van Assche wrote:
> That means that two buffers allocated with kmalloc() may share a cache line on
> x86-64. Since it is allowed to use a buffer allocated by kmalloc() for DMA, can
> this lead to data corruption, e.g. if the CPU writes into one buffer allocated
> with kmalloc() and a device performs a DMA write to another kmalloc() buffer and
> both write operations affect the same cache line?
You're not supposed to use kmalloc memory for DMA. This is why we have
dma_alloc_coherent() and friends. Also, from DMA-API.txt:
Memory coherency operates at a granularity called the cache
line width. In order for memory mapped by this API to operate
correctly, the mapped region must begin exactly on a cache line
boundary and end exactly on one (to prevent two separately mapped
regions from sharing a single cache line). Since the cache line size
may not be known at compile time, the API will not enforce this
requirement. Therefore, it is recommended that driver writers who
don't take special care to determine the cache line size at run time
only map virtual regions that begin and end on page boundaries (which
are guaranteed also to be cache line boundaries).
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