linux-kernel - Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

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Date:   Wed, 3 Oct 2018 17:41:32 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     Kan Liang <kan.liang@...ux.intel.com>, mingo@...hat.com,
        acme@...nel.org, linux-kernel@...r.kernel.org, eranian@...gle.com,
        ak@...ux.intel.com, alexander.shishkin@...ux.intel.com
Subject: Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

On Wed, Oct 03, 2018 at 08:10:31AM +0200, Thomas Gleixner wrote:
> On Tue, 2 Oct 2018, kan.liang@...ux.intel.com wrote:
> 
> There is another variant of model/stepping micro code verification code in
> intel_snb_pebs_broken(). Can we please make this table based and use a
> common function? That's certainly not the last quirk we're going to have.
> 
> We already have a table based variant of ucode checking in
> bad_spectre_microcode(). It's trivial enough to generalize that.

apic_check_deadline_errata() is another one. That one already uses the
x86_cpu_id thing, but still plays silly games for steppings. So if we're
going to build a new microcode table matcher...