linux-kernel - Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

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Message-ID: <20181003143300.GH32651@tassilo.jf.intel.com>
Date:   Wed, 3 Oct 2018 07:33:00 -0700
From:   Andi Kleen <ak@...ux.intel.com>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     Kan Liang <kan.liang@...ux.intel.com>, peterz@...radead.org,
        mingo@...hat.com, acme@...nel.org, linux-kernel@...r.kernel.org,
        eranian@...gle.com, alexander.shishkin@...ux.intel.com
Subject: Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

> There is another variant of model/stepping micro code verification code in
> intel_snb_pebs_broken(). Can we please make this table based and use a
> common function? That's certainly not the last quirk we're going to have.

I have a patch to add a table driven microcode matcher for another fix.
Will post shortly.

-Andi