linux-kernel - Re: [PATCH] reset: socfpga: add an early reset driver for SoCFPGA

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Message-ID: <04f701c1-8f1c-ee99-6797-cfbe769ebbc7@kernel.org>
Date:   Fri, 5 Oct 2018 10:17:10 -0500
From:   Dinh Nguyen <dinguyen@...nel.org>
To:     Philipp Zabel <p.zabel@...gutronix.de>
Cc:     marex@...x.de, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] reset: socfpga: add an early reset driver for SoCFPGA



On 10/04/2018 04:53 AM, Philipp Zabel wrote:
> Hi Dinh,
> 
> On Mon, 2018-09-17 at 09:50 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in reset-simple.
>> The reset driver for the SoCFPGA platform needs to register early in order to
>> be able bring online timers that needed early in the kernel bootup.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
>> ---
>>  arch/arm/mach-socfpga/socfpga.c |  4 ++
>>  drivers/reset/Kconfig           |  7 ++++
>>  drivers/reset/Makefile          |  1 +
>>  drivers/reset/reset-simple.c    | 17 ---------
>>  drivers/reset/reset-socfpga.c   | 85 +++++++++++++++++++++++++++++++++++++++++
>>  5 files changed, 97 insertions(+), 17 deletions(-)
>>  create mode 100644 drivers/reset/reset-socfpga.c
>>
>> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
>> index dde14f7..cc64576 100644
>> --- a/arch/arm/mach-socfpga/socfpga.c
>> +++ b/arch/arm/mach-socfpga/socfpga.c
>> @@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr;
>>  void __iomem *sdr_ctl_base_addr;
>>  unsigned long socfpga_cpu1start_addr;
>>  
>> +extern void __init socfpga_reset_init(void);
>> +
>>  void __init socfpga_sysmgr_init(void)
>>  {
>>  	struct device_node *np;
>> @@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void)
>>  
>>  	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
>>  		socfpga_init_ocram_ecc();
>> +	socfpga_reset_init();
>>  }
>>  
>>  static void __init socfpga_arria10_init_irq(void)
>> @@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void)
>>  		socfpga_init_arria10_l2_ecc();
>>  	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
>>  		socfpga_init_arria10_ocram_ecc();
>> +	socfpga_reset_init();
>>  }
>>  
>>  static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 13d28fd..dcc5f1d 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -119,6 +119,13 @@ config RESET_STM32MP157
>>  	help
>>  	  This enables the RCC reset controller driver for STM32 MPUs.
>>  
>> +config RESET_SOCFPGA
>> +	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
>> +	default ARCH_SOCFPGA
>> +	select RESET_SIMPLE
>> +	help
>> +	  This enables the reset driver for SoCFPGA.
>> +
>>  config RESET_SUNXI
>>  	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
>>  	default ARCH_SUNXI
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 4243c38..d09bb41 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>>  obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>>  obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>>  obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
>> +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
>>  obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>>  obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
>>  obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
>> diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
>> index a91107f..483824f 100644
>> --- a/drivers/reset/reset-simple.c
>> +++ b/drivers/reset/reset-simple.c
>> @@ -106,21 +106,12 @@ struct reset_simple_devdata {
>>  	bool status_active_low;
>>  };
>>  
>> -#define SOCFPGA_NR_BANKS	8
>> -
>> -static const struct reset_simple_devdata reset_simple_socfpga = {
>> -	.reg_offset = 0x10,
> 
> Before, the default reg_offset for DTs missing the altr,modrst-offset
> property was 0x10 ...
> 
>> -	.nr_resets = SOCFPGA_NR_BANKS * 32,
>> -	.status_active_low = true,
>> -};
>> -
> [...]
>> +static int a10_reset_init(struct device_node *np)
>> +{
>> +	struct reset_simple_data *data;
>> +	struct resource res;
>> +	resource_size_t size;
>> +	int ret;
>> +	u32 reg_offset = 0;
> 
> ... now it is 0x0.
> I think this should be
> 
> 	u32 reg_offset = 0x10;
> 
> to avoid breaking SocFPGA with ancient device trees.
> 
>> +
>> +	data = kzalloc(sizeof(*data), GFP_KERNEL);
>> +	if (!data)
>> +		return -ENOMEM;
>> +
>> +	ret = of_address_to_resource(np, 0, &res);
>> +	if (ret)
>> +		goto err_alloc;
>> +
>> +	size = resource_size(&res);
>> +	if (!request_mem_region(res.start, size, np->name)) {
>> +		ret = -EBUSY;
>> +		goto err_alloc;
>> +	}
>> +
>> +	data->membase = ioremap(res.start, size);
>> +	if (!data->membase) {
>> +		ret = -ENOMEM;
>> +		goto err_alloc;
>> +	}
>> +
>> +	if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))
>> +		pr_warn("missing altr,modrst-offset property, assuming 0x0\n");
>> +	data->membase += reg_offset;
>> +
>> +	spin_lock_init(&data->lock);
>> +
>> +	data->rcdev.owner = THIS_MODULE;
>> +	data->rcdev.nr_resets = 32 * 8;
> 
> Could we keep the SOCFPGA_NR_BANKS #define to reduce the amount of magic
> numbers?
> 
> I can make both changes when applying if you want.
> 

If you don't mind, that would be great!

Thanks,
Dinh