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Message-ID: <20181018143132.vhhc6qpz4sooljlj@lakrids.cambridge.arm.com>
Date:   Thu, 18 Oct 2018 15:31:32 +0100
From:   Mark Rutland <mark.rutland@....com>
To:     Nickhu <nickhu@...estech.com>
Cc:     greentime@...estech.com, linux-kernel@...r.kernel.org,
        robh+dt@...nel.org, deanbo422@...il.com, peterz@...radead.org,
        mingo@...hat.com, acme@...nel.org,
        alexander.shishkin@...ux.intel.com, jolsa@...hat.com,
        namhyung@...nel.org, arnd@...db.de, sboyd@...eaurora.org,
        geert@...ux-m68k.org, zong@...estech.com, ebiederm@...ssion.com,
        akpm@...ux-foundation.org, gregkh@...uxfoundation.org,
        pombredanne@...b.com, tglx@...utronix.de,
        kstewart@...uxfoundation.org, devicetree@...r.kernel.org,
        green.hu@...il.com
Subject: Re: [PATCH 5/5] nds32: Add document for NDS32 PMU.

On Thu, Oct 18, 2018 at 04:43:17PM +0800, Nickhu wrote:
> The document for how to add NDS32 PMU
> in devicetree.
> 
> Signed-off-by: Nickhu <nickhu@...estech.com>
> ---
>  Documentation/devicetree/bindings/nds32/pmu.txt | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/nds32/pmu.txt
> 
> diff --git a/Documentation/devicetree/bindings/nds32/pmu.txt b/Documentation/devicetree/bindings/nds32/pmu.txt
> new file mode 100644
> index 000000000000..02762b850e59
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nds32/pmu.txt
> @@ -0,0 +1,17 @@
> +* NDS32 Performance Monitor Units
> +
> +NDS32 core have a PMU for counting cpu and cache events like cache misses.
> +The NDS32 PMU representation in the device tree should be done as under:
> +
> +Required properties:
> +
> +- compatilbe :
> +	"andestech,atcpmu"

Which CPUs have this PMU?

I expected more specific strings, e.g. "andestech,n13-pmu" and/or
"andestech,andestech,nds32v3-pmu".

> +
> +- interrupts : The interrupt number for NDS32 PMU is 13.
> +
> +Example:
> +pmu{
> +	compatible = "andestech,atcpmu";
> +	interrupts = <13>;
> +}

The driver tried to find multiple interrupts. Is there only a single
interrupt in all cases?

Thanks,
Mark.

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