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Message-ID: <10a0572db79ef0cb4f345c8ba2685bea5670b1a5.camel@baylibre.com>
Date: Wed, 24 Oct 2018 10:58:56 +0200
From: Jerome Brunet <jbrunet@...libre.com>
To: Jianxin Pan <jianxin.pan@...ogic.com>,
Neil Armstrong <narmstrong@...libre.com>
Cc: Yixun Lan <yixun.lan@...ogic.com>,
Kevin Hilman <khilman@...libre.com>,
Carlo Caione <carlo@...one.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Boris Brezillon <boris.brezillon@...tlin.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Liang Yang <liang.yang@...ogic.com>,
Jian Hu <jian.hu@...ogic.com>,
Qiufang Dai <qiufang.dai@...ogic.com>,
Hanjie Lin <hanjie.lin@...ogic.com>,
Victor Wan <victor.wan@...ogic.com>, linux-clk@...r.kernel.org,
linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v5 1/3] clk: meson: add emmc sub clock phase delay driver
On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> From: Yixun Lan <yixun.lan@...ogic.com>
>
> Export the emmc sub clock phase delay ops which will be used
> by the emmc sub clock driver itself.
>
> Signed-off-by: Yixun Lan <yixun.lan@...ogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@...ogic.com>
> ---
> drivers/clk/meson/Makefile | 2 +-
> drivers/clk/meson/clk-phase-delay.c | 79 +++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/clkc.h | 13 ++++++
> 3 files changed, 93 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/meson/clk-phase-delay.c
>
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 72ec8c4..39ce566 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -2,7 +2,7 @@
> # Makefile for Meson specific clk
> #
>
> -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o clk-phase-delay.o
> obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
> obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c
> new file mode 100644
> index 0000000..b9573a7
> --- /dev/null
> +++ b/drivers/clk/meson/clk-phase-delay.c
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Amlogic Meson MMC Sub Clock Controller Driver
> + *
> + * Copyright (c) 2017 Baylibre SAS.
> + * Author: Jerome Brunet <jbrunet@...libre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yixun Lan <yixun.lan@...ogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include "clkc.h"
> +
> +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_clk_phase_delay_data *ph =
> + meson_clk_get_phase_delay_data(clk);
> + unsigned long period_ps, p, d;
> + int degrees;
> + u32 val;
> +
> + regmap_read(clk->map, ph->phase.reg_off, &val);
> + p = PARM_GET(ph->phase.width, ph->phase.shift, val);
there is an helper for this: meson_parm_read()
> + degrees = p * 360 / (1 << (ph->phase.width));
> +
> + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
> + clk_hw_get_rate(hw));
> +
> + d = PARM_GET(ph->delay.width, ph->delay.shift, val);
> + degrees += d * ph->delay_step_ps * 360 / period_ps;
> + degrees %= 360;
> +
> + return degrees;
> +}
> +
> +static void meson_clk_apply_phase_delay(struct clk_regmap *clk,
> + unsigned int phase,
> + unsigned int delay)
This helper function is a bit overkill.
simply call meson_parm_write() twice in meson_clk_phase_delay_set_phase().
> +{
> + struct meson_clk_phase_delay_data *ph = clk->data;
> + u32 val;
> +
> + regmap_read(clk->map, ph->delay.reg_off, &val);
> + val = PARM_SET(ph->phase.width, ph->phase.shift, val, phase);
> + val = PARM_SET(ph->delay.width, ph->delay.shift, val, delay);
> + regmap_write(clk->map, ph->delay.reg_off, val);
> +}
> +
> +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_clk_phase_delay_data *ph =
> + meson_clk_get_phase_delay_data(clk);
> + unsigned long period_ps, d = 0, r;
> + u64 p;
> +
> + p = degrees % 360;
> + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
> + clk_hw_get_rate(hw));
> +
> + /* First compute the phase index (p), the remainder (r) is the
> + * part we'll try to acheive using the delays (d).
> + */
> + r = do_div(p, 360 / (1 << (ph->phase.width)));
> + d = DIV_ROUND_CLOSEST(r * period_ps,
> + 360 * ph->delay_step_ps);
> + d = min(d, PMASK(ph->delay.width));
> +
> + meson_clk_apply_phase_delay(clk, p, d);
> + return 0;
> +}
> +
> +const struct clk_ops meson_clk_phase_delay_ops = {
> + .get_phase = meson_clk_phase_delay_get_phase,
> + .set_phase = meson_clk_phase_delay_set_phase,
> +};
> +EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index 6b96d55..3309d78 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -105,6 +105,18 @@ struct clk_regmap _name = { \
> }, \
> };
>
> +struct meson_clk_phase_delay_data {
> + struct parm phase;
> + struct parm delay;
> + unsigned int delay_step_ps;
> +};
> +
> +static inline struct meson_clk_phase_delay_data *
> +meson_clk_get_phase_delay_data(struct clk_regmap *clk)
> +{
> + return (struct meson_clk_phase_delay_data *)clk->data;
> +}
> +
> /* clk_ops */
> extern const struct clk_ops meson_clk_pll_ro_ops;
> extern const struct clk_ops meson_clk_pll_ops;
> @@ -112,5 +124,6 @@ struct clk_regmap _name = { \
> extern const struct clk_ops meson_clk_mpll_ro_ops;
> extern const struct clk_ops meson_clk_mpll_ops;
> extern const struct clk_ops meson_clk_phase_ops;
> +extern const struct clk_ops meson_clk_phase_delay_ops;
>
> #endif /* __CLKC_H */
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