linux-kernel - [tip:x86/urgent] x86/cpufeatures: Enumerate MOVDIR64B instruction

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Message-ID: <tip-ace6485a03266cc3c198ce8e927a1ce0ce139699@git.kernel.org>
Date:   Wed, 24 Oct 2018 22:46:33 -0700
From:   tip-bot for Fenghua Yu <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, dvlasenk@...hat.com, fenghua.yu@...el.com,
        ashok.raj@...el.com, peterz@...radead.org, bp@...en8.de,
        ravi.v.shankar@...el.com, mingo@...nel.org,
        linux-kernel@...r.kernel.org, brgerst@...il.com,
        torvalds@...ux-foundation.org, hpa@...or.com, luto@...capital.net
Subject: [tip:x86/urgent] x86/cpufeatures: Enumerate MOVDIR64B instruction

Commit-ID:  ace6485a03266cc3c198ce8e927a1ce0ce139699
Gitweb:     https://git.kernel.org/tip/ace6485a03266cc3c198ce8e927a1ce0ce139699
Author:     Fenghua Yu <fenghua.yu@...el.com>
AuthorDate: Wed, 24 Oct 2018 14:57:17 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 25 Oct 2018 07:42:48 +0200

x86/cpufeatures: Enumerate MOVDIR64B instruction

MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
Direct store is implemented by using write combining (WC) for writing
data directly into memory without caching the data.

In low latency offload (e.g. Non-Volatile Memory, etc), MOVDIR64B writes
work descriptors (and data in some cases) to device-hosted work-queues
atomically without cache pollution.

Availability of the MOVDIR64B instruction is indicated by the
presence of the CPUID feature flag MOVDIR64B (CPUID.0x07.0x0:ECX[bit 28]).

Please check the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference for more details on the CPUID
feature MOVDIR64B flag.

Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
Cc: Andy Lutomirski <luto@...capital.net>
Cc: Ashok Raj <ashok.raj@...el.com>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Brian Gerst <brgerst@...il.com>
Cc: Denys Vlasenko <dvlasenk@...hat.com>
Cc: H. Peter Anvin <hpa@...or.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Ravi V Shankar <ravi.v.shankar@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: http://lkml.kernel.org/r/1540418237-125817-3-git-send-email-fenghua.yu@intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 90934ee7b79a..28c4a502b419 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -332,6 +332,7 @@
 #define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
 #define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */
 #define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */
+#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
 #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */