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Message-ID: <CACRpkdbXPWH4FS5205ML0UmuATuZf087Y6ueVUdp_Lfc5Nu8Hw@mail.gmail.com>
Date: Thu, 25 Oct 2018 12:16:32 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: svendev@...x.com
Cc: Lee Jones <lee.jones@...aro.org>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Andreas Färber <afaerber@...e.de>,
Thierry Reding <treding@...dia.com>,
David Lechner <david@...hnology.com>,
Noralf Trønnes <noralf@...nnes.org>,
Johan Hovold <johan@...nel.org>,
Michal Simek <monstr@...str.eu>, michal.vokac@...ft.com,
Arnd Bergmann <arnd@...db.de>,
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Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Robin Murphy <robin.murphy@....com>,
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"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>
Subject: Re: [PATCH anybus v1 2/4] dt-bindings: anybus-bridge: document
devicetree binding.
Hi Sven,
thanks for your patch!
On Wed, Oct 24, 2018 at 4:25 PM Sven Van Asbroeck <svendev@...x.com> wrote:
> + - pwms : the pwm connected to the bridge's 'pwm input'.
That is really unintuitive and needs a detailed explanation. What
is a bridge doing with a PWM? Is it 100% certain this is a PWM,
it's not just a .... clock? A pwm is a pule WIDTH modulator and
I can't for my life understand why a bus bridge needs a signal
with variable pulse width, but surprise me! :D
> + fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
> + 0x00000000 0xa0000240 0x00000000>;
Is it just a copy/paste from
Documentation/devicetree/bindings/bus/imx-weim.txt
leftover?
It was mentioned as undocumented but it is also pretty terse
with these opaque hex numbers. I would never let the
Freescale binding pass if I was reviewing it.
Look at my bindings for Qualcomm EBI in
Documentation/devicetree/bindings/bus/qcom,ebi2.txt
for example.
But maybe it's not even supposed to be there.
Yours,
Linus Walleij
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