linux-kernel - Re: [PATCH v3 1/3] mfd: upboard: Add UP2 platform controller driver

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Message-ID: <32536c5d-9e88-7b2b-d7ab-acb2247870fa@emutex.com>
Date:   Thu, 1 Nov 2018 09:58:19 +0000
From:   Dan O'Donovan <dan.odonovan@...tex.com>
To:     Lee Jones <lee.jones@...aro.org>,
        Dan O'Donovan <dan.odonovan@...tex.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Mika Westerberg <mika.westerberg@...ux.intel.com>,
        Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Jacek Anaszewski <jacek.anaszewski@...il.com>,
        Pavel Machek <pavel@....cz>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-leds@...r.kernel.org" <linux-leds@...r.kernel.org>,
        Carlos Iglesias <carlos.iglesias@...tex.com>
Subject: Re: [PATCH v3 1/3] mfd: upboard: Add UP2 platform controller driver

On 11/01/2018 08:07 AM, Lee Jones wrote:
> On Wed, 31 Oct 2018, Dan O'Donovan wrote:
>
>> UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
>> features a MAX 10 FPGA that routes lines from both SoC and on-board
>> devices to two I/O headers:
>>
>>                                 +------------------------+
>>                                 | 40-pin RPi-like header |
>>                          +------|         (HAT)          |
>>                          |      +------------------------+
>>     +-------+    +--------+
>>     |       |    |        |     +------------------------+
>>     |  SoC  |----|  FPGA  |-----|  Custom UP2 pin header |
>>     |       |    |        |     |        (EXHAT)         |
>>     +-------+    +--------+     +------------------------+
>>                          |
>>                          +------* On-board devices: LED, VLS...
>>
>> This is intended to enable vendor-specific applications to customize I/O
>> header pinout, as well as include low-latency functionality. It also
>> performs voltage level translation between the SoC (1.8V) and HAT header
>> (3.3V).
>>
>> Out of the box, this block implements a platform controller with a
>> GPIO-bitbanged control interface. It's enumerated by ACPI and provides
>> registers to control:
>>
>> - Configuration of all FPGA-routed header lines. These can be driven
>>   SoC-to-header, header-to-SoC or set in high impedance.
>>
>> - On-board LEDs and enable lines for other platform devices.
>>
>> Add core support for this platform controller as a MFD device, exposing
>> these registers as a regmap.
>>
>> Acked-by: Linus Walleij <linus.walleij@...aro.org>
>> Signed-off-by: Dan O'Donovan <dan@...tex.com>
>> ---
>>  drivers/mfd/Kconfig         |  17 +++
>>  drivers/mfd/Makefile        |   1 +
>>  drivers/mfd/upboard.c       | 336 ++++++++++++++++++++++++++++++++++++++++++++
>>  include/linux/mfd/upboard.h |  44 ++++++
>>  4 files changed, 398 insertions(+)
>>  create mode 100644 drivers/mfd/upboard.c
>>  create mode 100644 include/linux/mfd/upboard.h
> Looks like you've ignored the review comments here too.
Hi Lee.  Looks like I didn't receive your original email, most likely because of a crappy spam filtering service we were using here up until recently.  I've found your comments in online archives now and will address them in the next revision of the patches.  Sorry for the inconvenience. :(