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Message-ID: <CACRpkdZRi_prZK=EwFF86bWEC26+ajr9F9s3ALqVi-rQW+r2AQ@mail.gmail.com>
Date:   Fri, 9 Nov 2018 10:59:20 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     marek.behun@....cz
Cc:     ext Tony Lindgren <tony@...mide.com>,
        Shawn Guo <shawnguo@...nel.org>, Rob Herring <robh@...nel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 bus+gpio 1/4] bus: Add support for Moxtet bus

On Fri, Nov 2, 2018 at 11:35 AM Marek BehĂșn <marek.behun@....cz> wrote:

> On the Turris Mox router different modules can be connected to the main
> CPU board: currently a module with a SFP cage, a module with MiniPCIe
> connector, a 4-port switch module, an 8-port switch module, and a 4-port
> USB3 module.
>
> For example:
>   [CPU]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]
>
> Each of this modules has an input and output shift register, and these
> are connected via SPI to the CPU board.
>
> Via SPI we are able to discover which modules are connected, in which
> order, and we can also read some information about the modules or
> configure them.
> From each module 8 bits can be read (of which low 4 bits identify the
> module) and 8 bits can be written.
>
> For example from the module with a SFP cage we can read the LOS,
> TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and
> RATE-SELECT signals.
>
> This driver creates a new bus type, called "moxtet". For each Mox module
> it finds via SPI, it creates a new device on the moxtet bus so that
> drivers can be written for them.
>
> The topology of how Mox modules are connected can then be read by
> listing /sys/bus/moxtet/devices.
>
> Signed-off-by: Marek BehĂșn <marek.behun@....cz>

This looks fine to me. Maybe strange with "gpio" in the
subject of the mail? Consider adding sysfs ABI documentation
in Documentation/ABI/testing/*
Acked-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij

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