linux-kernel - Re: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD

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Message-ID: <204f5ddb-21f3-5275-273b-02335a5a03c8@amd.com>
Date:   Wed, 14 Nov 2018 18:17:25 +0000
From:   "Moger, Babu" <Babu.Moger@....com>
To:     "Yu, Fenghua" <fenghua.yu@...el.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>, "corbet@....net" <corbet@....net>,
        "Chatre, Reinette" <reinette.chatre@...el.com>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "akpm@...ux-foundation.org" <akpm@...ux-foundation.org>
CC:     "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "mchehab+samsung@...nel.org" <mchehab+samsung@...nel.org>,
        "arnd@...db.de" <arnd@...db.de>,
        "kstewart@...uxfoundation.org" <kstewart@...uxfoundation.org>,
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        "rafael@...nel.org" <rafael@...nel.org>,
        "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
        "Luck, Tony" <tony.luck@...el.com>,
        "qianyue.zj@...baba-inc.com" <qianyue.zj@...baba-inc.com>,
        "Shen, Xiaochen" <xiaochen.shen@...el.com>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "Singh, Brijesh" <brijesh.singh@....com>,
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        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "Hunt, Douglas" <Douglas.Hunt@....com>
Subject: Re: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD



On 11/14/18 10:38 AM, Moger, Babu wrote:
> Fenghua,
> 
>> -----Original Message-----
>> From: linux-kernel-owner@...r.kernel.org <linux-kernel-
>> owner@...r.kernel.org> On Behalf Of Yu, Fenghua
>> Sent: Tuesday, November 13, 2018 3:50 PM
>> To: Moger, Babu <Babu.Moger@....com>; tglx@...utronix.de;
>> mingo@...hat.com; bp@...en8.de; corbet@....net; Chatre, Reinette
>> <reinette.chatre@...el.com>; peterz@...radead.org;
>> gregkh@...uxfoundation.org; davem@...emloft.net; akpm@...ux-
>> foundation.org
>> Cc: hpa@...or.com; x86@...nel.org; mchehab+samsung@...nel.org;
>> arnd@...db.de; kstewart@...uxfoundation.org; pombredanne@...b.com;
>> rafael@...nel.org; kirill.shutemov@...ux.intel.com; Luck, Tony
>> <tony.luck@...el.com>; qianyue.zj@...baba-inc.com; Shen, Xiaochen
>> <xiaochen.shen@...el.com>; pbonzini@...hat.com; Singh, Brijesh
>> <brijesh.singh@....com>; Hurwitz, Sherry <sherry.hurwitz@....com>;
>> dwmw2@...radead.org; Lendacky, Thomas <Thomas.Lendacky@....com>;
>> luto@...nel.org; joro@...tes.org; jannh@...gle.com;
>> vkuznets@...hat.com; rian@...m.mit.edu; jpoimboe@...hat.com; linux-
>> kernel@...r.kernel.org; linux-doc@...r.kernel.org; Yu, Fenghua
>> <fenghua.yu@...el.com>
>> Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
>>
>>> From: Moger, Babu [mailto:Babu.Moger@....com]
>>> Subject: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
>>> The specification for this feature is available at
>>> https://developer.amd.com/wp-content/resources/56375.pdf
>>
>>> +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r) {
>>> +	if (val > r->default_ctrl) {
>>> +		rdt_last_cmd_puts("mask out of range\n");
>>> +		return false;
>>> +	}
>>
>> If val is zero, then this closid cannot allocate any cache line.
>>
>> I'm wondering: does that mean the tasks running with this closid directly
>> access memory without cache? Is there any usage for this situation?

Here is the detailed answer to your question from Doug(in CC).

A closid with L3_MASK of all 0's will not use any of the L3 cache, but
will still be able to use L2 cache.  So, no, the processes in that closid
will not "directly access memory" in the sense that they will use the L1
and L2 caches as normal.  But if they miss the L2 then, yes, the access
will go directly to memory.  To be precise, none of the lines which are
fetched by a process running with such a configuration will be installed
in the L3 cache, so subsequent accesses which miss the L2 cache will not
find the requested data in the L3 cache and will then go on to access memory.

- Doug

> 
> I would think any memory access has to happen via cache only.  But
> I am not sure about the usage of this situation. Will check on that.
> Will post if I get any more information. But I can say that it is
> allowed to have mask as zero. Looking at the specs
> https://developer.amd.com/wp-content/resources/56375.pdf
> 
> The bits which are set in the various L3_MASK_n registers do not have to be
> contiguous and may overlap in any desired combination. If an L3_MASK_n
> register is programmed with all 0's, that COS will be prevented from allocating
> any lines in the L3 cache. At reset, all L3_MASK_n registers are initialized to all
> 1's, allowing all processors to use the entire L3 cache accessible to them.
> 
>>
>> Thanks.
>>
>> -Fenghua