linux-kernel - RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD

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Message-ID: <DM5PR12MB2471AB9EFDE9E8D7C65C58A295C30@DM5PR12MB2471.namprd12.prod.outlook.com>
Date:   Wed, 14 Nov 2018 16:38:56 +0000
From:   "Moger, Babu" <Babu.Moger@....com>
To:     "Yu, Fenghua" <fenghua.yu@...el.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
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Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD

Fenghua,

> -----Original Message-----
> From: linux-kernel-owner@...r.kernel.org <linux-kernel-
> owner@...r.kernel.org> On Behalf Of Yu, Fenghua
> Sent: Tuesday, November 13, 2018 3:50 PM
> To: Moger, Babu <Babu.Moger@....com>; tglx@...utronix.de;
> mingo@...hat.com; bp@...en8.de; corbet@....net; Chatre, Reinette
> <reinette.chatre@...el.com>; peterz@...radead.org;
> gregkh@...uxfoundation.org; davem@...emloft.net; akpm@...ux-
> foundation.org
> Cc: hpa@...or.com; x86@...nel.org; mchehab+samsung@...nel.org;
> arnd@...db.de; kstewart@...uxfoundation.org; pombredanne@...b.com;
> rafael@...nel.org; kirill.shutemov@...ux.intel.com; Luck, Tony
> <tony.luck@...el.com>; qianyue.zj@...baba-inc.com; Shen, Xiaochen
> <xiaochen.shen@...el.com>; pbonzini@...hat.com; Singh, Brijesh
> <brijesh.singh@....com>; Hurwitz, Sherry <sherry.hurwitz@....com>;
> dwmw2@...radead.org; Lendacky, Thomas <Thomas.Lendacky@....com>;
> luto@...nel.org; joro@...tes.org; jannh@...gle.com;
> vkuznets@...hat.com; rian@...m.mit.edu; jpoimboe@...hat.com; linux-
> kernel@...r.kernel.org; linux-doc@...r.kernel.org; Yu, Fenghua
> <fenghua.yu@...el.com>
> Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
> 
> > From: Moger, Babu [mailto:Babu.Moger@....com]
> > Subject: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
> > The specification for this feature is available at
> > https://developer.amd.com/wp-content/resources/56375.pdf
> 
> > +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r) {
> > +	if (val > r->default_ctrl) {
> > +		rdt_last_cmd_puts("mask out of range\n");
> > +		return false;
> > +	}
> 
> If val is zero, then this closid cannot allocate any cache line.
> 
> I'm wondering: does that mean the tasks running with this closid directly
> access memory without cache? Is there any usage for this situation?

I would think any memory access has to happen via cache only.  But
I am not sure about the usage of this situation. Will check on that.
Will post if I get any more information. But I can say that it is
allowed to have mask as zero. Looking at the specs
https://developer.amd.com/wp-content/resources/56375.pdf

The bits which are set in the various L3_MASK_n registers do not have to be
contiguous and may overlap in any desired combination. If an L3_MASK_n
register is programmed with all 0's, that COS will be prevented from allocating
any lines in the L3 cache. At reset, all L3_MASK_n registers are initialized to all
1's, allowing all processors to use the entire L3 cache accessible to them.

> 
> Thanks.
> 
> -Fenghua