linux-kernel - RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD

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Message-ID: <3E5A0FA7E9CA944F9D5414FEC6C71220985A68FF@ORSMSX105.amr.corp.intel.com>
Date:   Wed, 14 Nov 2018 19:31:01 +0000
From:   "Yu, Fenghua" <fenghua.yu@...el.com>
To:     "Moger, Babu" <Babu.Moger@....com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
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        "akpm@...ux-foundation.org" <akpm@...ux-foundation.org>
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        "Hunt, Douglas" <Douglas.Hunt@....com>
Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD

> From: Moger, Babu [mailto:Babu.Moger@....com]
> >> I'm wondering: does that mean the tasks running with this closid
> >> directly access memory without cache? Is there any usage for this
> situation?
> 
> Here is the detailed answer to your question from Doug(in CC).
> 
> A closid with L3_MASK of all 0's will not use any of the L3 cache, but will still
> be able to use L2 cache.  So, no, the processes in that closid will not
> "directly access memory" in the sense that they will use the L1 and L2
> caches as normal.  But if they miss the L2 then, yes, the access will go
> directly to memory.  To be precise, none of the lines which are fetched by a
> process running with such a configuration will be installed in the L3 cache,
> so subsequent accesses which miss the L2 cache will not find the requested
> data in the L3 cache and will then go on to access memory.

Seems all zeros CBM reduces the caches to L1 and L2. This might be useful in fast access to small data fitting in L2.

Thank you very much for your explanation!

-Fenghua