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Message-ID: <3c7e275e-c833-cfbf-813e-d71858bbef63@nvidia.com>
Date: Mon, 19 Nov 2018 21:27:32 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Dmitry Osipenko <digetx@...il.com>,
Thierry Reding <thierry.reding@...il.com>,
Peter De Schrijver <pdeschrijver@...dia.com>
CC: <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on
resume from LP1 on Tegra30+
On 30/08/2018 19:54, Dmitry Osipenko wrote:
> The memory interface configuration and re-calibration interval are left
> unassigned on resume from LP1 because these registers are shadowed and
> require latching after being adjusted.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> arch/arm/mach-tegra/sleep-tegra30.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
> index 127fc78365fe..801fe58978ae 100644
> --- a/arch/arm/mach-tegra/sleep-tegra30.S
> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
> @@ -521,6 +521,8 @@ zcal_done:
> ldr r1, [r5, #0x0] @ restore EMC_CFG
> str r1, [r0, #EMC_CFG]
>
> + emc_timing_update r1, r0
> +
> /* Tegra114 had dual EMC channel, now config the other one */
> cmp r10, #TEGRA114
> bne __no_dual_emc_chanl
>
This is stated in the TRM as what needs to be done. So ...
Reviewed-by: Jon Hunter <jonathanh@...dia.com>
Cheers
Jon
--
nvpublic
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