lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 21 Nov 2018 09:51:30 -0300
From:   Arnaldo Carvalho de Melo <acme@...nel.org>
To:     Jiri Olsa <jolsa@...hat.com>
Cc:     "Liang, Kan" <kan.liang@...ux.intel.com>, mingo@...hat.com,
        peterz@...radead.org, linux-kernel@...r.kernel.org,
        namhyung@...nel.org, ak@...ux.intel.com
Subject: Re: [PATCH 2/2] perf vendor events: Add JSON metrics for Cascadelake
 server

Em Thu, Nov 15, 2018 at 04:14:42PM +0100, Jiri Olsa escreveu:
> On Thu, Nov 15, 2018 at 08:33:27AM -0500, Liang, Kan wrote:
> > 
> > 
> > On 11/15/2018 8:21 AM, Jiri Olsa wrote:
> > > On Wed, Nov 14, 2018 at 01:24:16PM -0800, kan.liang@...ux.intel.com wrote:
> > > > From: Kan Liang <kan.liang@...ux.intel.com>
> > > > 
> > > > Add JSON metrics (based on event list v1) for Cascadelake server
> > > 
> > > hum mail server probably crippled the email so it won't apply:
> > > 
> > > patching file pmu-events/arch/x86/cascadelakex/cache.json
> > > patching file pmu-events/arch/x86/cascadelakex/clx-metrics.json
> > > patching file pmu-events/arch/x86/cascadelakex/floating-point.json
> > > patching file pmu-events/arch/x86/cascadelakex/frontend.json
> > > patching file pmu-events/arch/x86/cascadelakex/memory.json
> > > patching file pmu-events/arch/x86/cascadelakex/other.json
> > > patching file pmu-events/arch/x86/cascadelakex/pipeline.json
> > > patch: **** malformed patch at line 29879:  ow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
> > > 
> > > I've similar error before and it was because of the 998 chars size
> > > limit for line.. I guess you could either post it as attachment or
> > > change the transfer encoding
> > > 
> > 
> > The patch is attached. Can it be applied?
> 
> yep, that one works

Can I have your reviewed-by for this one as well?

- Arnaldo

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ