| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <tip-a36c5ff560fb32d17c020fa3e7f4c70f753d8834@git.kernel.org>
Date: Thu, 22 Nov 2018 13:48:50 -0800
From: tip-bot for Babu Moger <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: Thomas.Lendacky@....com, rafael@...nel.org, hpa@...or.com,
corbet@....net, dima@...sta.com, qianyue.zj@...baba-inc.com,
kstewart@...uxfoundation.org, bp@...e.de, mingo@...nel.org,
sherry.hurwitz@....com, tony.luck@...el.com, rian@...m.mit.edu,
dwmw2@...radead.org, kirill.shutemov@...ux.intel.com,
linux-kernel@...r.kernel.org, puwen@...on.cn,
reinette.chatre@...el.com, linux-doc@...r.kernel.org,
jpoimboe@...hat.com, davem@...emloft.net, arnd@...db.de,
vkuznets@...hat.com, xiaochen.shen@...el.com, pombredanne@...b.com,
babu.moger@....com, mchehab+samsung@...nel.org,
pbonzini@...hat.com, akpm@...ux-foundation.org,
chang.seok.bae@...el.com, brijesh.singh@....com, jannh@...gle.com,
Babu.Moger@....com, tglx@...utronix.de, mingo@...hat.com,
fenghua.yu@...el.com, luto@...nel.org, gregkh@...uxfoundation.org,
suravee.suthikulpanit@....com, jroedel@...e.de,
peterz@...radead.org
Subject: [tip:x86/cache] x86/resctrl: Bring cbm_validate() into the resource
structure
Commit-ID: a36c5ff560fb32d17c020fa3e7f4c70f753d8834
Gitweb: https://git.kernel.org/tip/a36c5ff560fb32d17c020fa3e7f4c70f753d8834
Author: Babu Moger <Babu.Moger@....com>
AuthorDate: Wed, 21 Nov 2018 20:28:35 +0000
Committer: Borislav Petkov <bp@...e.de>
CommitDate: Thu, 22 Nov 2018 20:16:19 +0100
x86/resctrl: Bring cbm_validate() into the resource structure
Bring all the functions that are different between the vendors into the
resource structure and initialize them dynamically. Add _intel suffix to
the Intel-specific functions.
cbm_validate() which does cache bitmask validation, differs between the
vendors as AMD allows non-contiguous masks. So, use separate functions
for Intel and AMD.
[ bp: Massage commit message and fixup rdt_resource members' vertical
alignment. ]
Signed-off-by: Babu Moger <babu.moger@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: Andrew Morton <akpm@...ux-foundation.org>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Arnd Bergmann <arnd@...db.de>
Cc: Brijesh Singh <brijesh.singh@....com>
Cc: "Chang S. Bae" <chang.seok.bae@...el.com>
Cc: David Miller <davem@...emloft.net>
Cc: David Woodhouse <dwmw2@...radead.org>
Cc: Dmitry Safonov <dima@...sta.com>
Cc: Fenghua Yu <fenghua.yu@...el.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: "H. Peter Anvin" <hpa@...or.com>
Cc: Ingo Molnar <mingo@...hat.com>
Cc: Jann Horn <jannh@...gle.com>
Cc: Joerg Roedel <jroedel@...e.de>
Cc: Jonathan Corbet <corbet@....net>
Cc: Josh Poimboeuf <jpoimboe@...hat.com>
Cc: Kate Stewart <kstewart@...uxfoundation.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
Cc: <linux-doc@...r.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab+samsung@...nel.org>
Cc: Paolo Bonzini <pbonzini@...hat.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Philippe Ombredanne <pombredanne@...b.com>
Cc: Pu Wen <puwen@...on.cn>
Cc: <qianyue.zj@...baba-inc.com>
Cc: "Rafael J. Wysocki" <rafael@...nel.org>
Cc: Reinette Chatre <reinette.chatre@...el.com>
Cc: Rian Hunter <rian@...m.mit.edu>
Cc: Sherry Hurwitz <sherry.hurwitz@....com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Thomas Lendacky <Thomas.Lendacky@....com>
Cc: Tony Luck <tony.luck@...el.com>
Cc: Vitaly Kuznetsov <vkuznets@...hat.com>
Cc: <xiaochen.shen@...el.com>
Link: https://lkml.kernel.org/r/20181121202811.4492-7-babu.moger@amd.com
---
arch/x86/kernel/cpu/resctrl/core.c | 9 ++++++++-
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 4 ++--
arch/x86/kernel/cpu/resctrl/internal.h | 15 +++++++++------
3 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 3bd245b057c4..ba5a5b8c4681 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -878,7 +878,14 @@ static __init void rdt_init_res_defs_intel(void)
struct rdt_resource *r;
for_each_rdt_resource(r) {
- if (r->rid == RDT_RESOURCE_MBA) {
+ if (r->rid == RDT_RESOURCE_L3 ||
+ r->rid == RDT_RESOURCE_L3DATA ||
+ r->rid == RDT_RESOURCE_L3CODE ||
+ r->rid == RDT_RESOURCE_L2 ||
+ r->rid == RDT_RESOURCE_L2DATA ||
+ r->rid == RDT_RESOURCE_L2CODE)
+ r->cbm_validate = cbm_validate_intel;
+ else if (r->rid == RDT_RESOURCE_MBA) {
r->msr_base = MSR_IA32_MBA_THRTL_BASE;
r->msr_update = mba_wrmsr_intel;
r->parse_ctrlval = parse_bw_intel;
diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
index a8ae87e756e9..d2e0b99d453f 100644
--- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
+++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
@@ -88,7 +88,7 @@ int parse_bw_intel(struct rdt_parse_data *data, struct rdt_resource *r,
* are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
* Additionally Haswell requires at least two bits set.
*/
-static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
+bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r)
{
unsigned long first_bit, zero_bit, val;
unsigned int cbm_len = r->cache.cbm_len;
@@ -148,7 +148,7 @@ int parse_cbm(struct rdt_parse_data *data, struct rdt_resource *r,
return -EINVAL;
}
- if (!cbm_validate(data->buf, &cbm_val, r))
+ if (r->cbm_validate && !r->cbm_validate(data->buf, &cbm_val, r))
return -EINVAL;
if ((rdtgrp->mode == RDT_MODE_EXCLUSIVE ||
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 9a643f444723..599cad34a6a8 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -396,9 +396,9 @@ struct rdt_parse_data {
* struct rdt_resource - attributes of an RDT resource
* @rid: The index of the resource
* @alloc_enabled: Is allocation enabled on this machine
- * @mon_enabled: Is monitoring enabled for this feature
+ * @mon_enabled: Is monitoring enabled for this feature
* @alloc_capable: Is allocation available on this machine
- * @mon_capable: Is monitor feature available on this machine
+ * @mon_capable: Is monitor feature available on this machine
* @name: Name to use in "schemata" file
* @num_closid: Number of CLOSIDs available
* @cache_level: Which cache level defines scope of this resource
@@ -410,10 +410,11 @@ struct rdt_parse_data {
* @cache: Cache allocation related data
* @format_str: Per resource format string to show domain value
* @parse_ctrlval: Per resource function pointer to parse control values
- * @evt_list: List of monitoring events
- * @num_rmid: Number of RMIDs available
- * @mon_scale: cqm counter * mon_scale = occupancy in bytes
- * @fflags: flags to choose base and info files
+ * @cbm_validate Cache bitmask validate function
+ * @evt_list: List of monitoring events
+ * @num_rmid: Number of RMIDs available
+ * @mon_scale: cqm counter * mon_scale = occupancy in bytes
+ * @fflags: flags to choose base and info files
*/
struct rdt_resource {
int rid;
@@ -436,6 +437,7 @@ struct rdt_resource {
int (*parse_ctrlval)(struct rdt_parse_data *data,
struct rdt_resource *r,
struct rdt_domain *d);
+ bool (*cbm_validate)(char *buf, u32 *data, struct rdt_resource *r);
struct list_head evt_list;
int num_rmid;
unsigned int mon_scale;
@@ -576,5 +578,6 @@ void cqm_setup_limbo_handler(struct rdt_domain *dom, unsigned long delay_ms);
void cqm_handle_limbo(struct work_struct *work);
bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d);
void __check_limbo(struct rdt_domain *d, bool force_free);
+bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r);
#endif /* _ASM_X86_RESCTRL_INTERNAL_H */
Powered by blists - more mailing lists