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Message-ID: <154386555833.88331.17771094561482296098@swboyd.mtv.corp.google.com>
Date: Mon, 03 Dec 2018 11:32:38 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: "A.s. Dong" <aisheng.dong@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"mturquette@...libre.com" <mturquette@...libre.com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
Anson Huang <anson.huang@....com>,
Jacky Bai <ping.bai@....com>, dl-linux-imx <linux-imx@....com>,
"A.s. Dong" <aisheng.dong@....com>,
Stephen Boyd <sboyd@...eaurora.org>
Subject: Re: [PATCH V6 9/9] clk: imx: add imx7ulp clk driver
Quoting A.s. Dong (2018-11-14 05:02:08)
> i.MX7ULP Clock functions are under joint control of the System
> Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
> modules, and Core Mode Controller (CMC)1 blocks
>
> The clocking scheme provides clear separation between M4 domain
> and A7 domain. Except for a few clock sources shared between two
> domains, such as the System Oscillator clock, the Slow IRC (SIRC),
> and and the Fast IRC clock (FIRCLK), clock sources and clock
> management are separated and contained within each domain.
>
> M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
> A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
>
> This driver only adds clock support in A7 domain.
>
> Note that most clocks required to be operated when gated, e.g. pll,
> pfd, pcc. And more special cases that scs/ddr/nic mux selecting
> different clock source requires that clock to be enabled first,
> then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
>
> Cc: Stephen Boyd <sboyd@...eaurora.org>
> Cc: Michael Turquette <mturquette@...libre.com>
> Cc: Shawn Guo <shawnguo@...nel.org>
> Cc: Anson Huang <Anson.Huang@....com>
> Cc: Bai Ping <ping.bai@....com>
> Signed-off-by: Dong Aisheng <aisheng.dong@....com>
>
> ---
Applied to clk-next
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