linux-kernel - RE: [PATCH V6 0/9] clk: add imx7ulp clk support

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Message-ID: <AM0PR04MB42111FFF525D6EC5D785692380AF0@AM0PR04MB4211.eurprd04.prod.outlook.com>
Date:   Tue, 4 Dec 2018 01:29:29 +0000
From:   Aisheng DONG <aisheng.dong@....com>
To:     Stephen Boyd <sboyd@...nel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Anson Huang <anson.huang@....com>,
        Jacky Bai <ping.bai@....com>, dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH V6 0/9] clk: add imx7ulp clk support

> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@...nel.org]
> Sent: Tuesday, December 4, 2018 3:32 AM
> To: Aisheng DONG <aisheng.dong@....com>; linux-clk@...r.kernel.org
> Cc: linux-kernel@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> mturquette@...libre.com; shawnguo@...nel.org; Anson Huang
> <anson.huang@....com>; Jacky Bai <ping.bai@....com>; dl-linux-imx
> <linux-imx@....com>; Aisheng DONG <aisheng.dong@....com>
> Subject: Re: [PATCH V6 0/9] clk: add imx7ulp clk support
> 
> Quoting A.s. Dong (2018-11-14 05:01:31)
> > This patch series intends to add imx7ulp clk support.
> >
> > i.MX7ULP Clock functions are under joint control of the System Clock
> > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and
> > Core Mode Controller (CMC)1 blocks
> >
> > The clocking scheme provides clear separation between M4 domain and A7
> > domain. Except for a few clock sources shared between two domains,
> > such as the System Oscillator clock, the Slow IRC (SIRC), and and the
> > Fast IRC clock (FIRCLK), clock sources and clock management are
> > separated and contained within each domain.
> >
> > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
> > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
> >
> > Note: this series only adds A7 clock domain support as M4 clock domain
> > will be handled by M4 seperately.
> >
> 
> I got:
> 
> drivers/clk/imx/clk-pllv4.c:152:15: warning: symbol 'imx_clk_pllv4' was not
> declared. Should it be static?
> drivers/clk/imx/clk-pfdv2.c:166:15: warning: symbol 'imx_clk_pfdv2' was not
> declared. Should it be static?
> drivers/clk/imx/clk-divider-gate.c:174:15: warning: symbol
> 'imx_clk_divider_gate' was not declared. Should it be static?
> drivers/clk/imx/clk-composite-7ulp.c:22:15: warning: symbol
> 'imx7ulp_clk_composite' was not declared. Should it be static?
> 
> which I can fix easily by throwing in clk.h into each file.

Thanks, I will double check it when I back to office.

Regards
Dong Aisheng