linux-kernel - Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 11 Dec 2018 15:35:45 +0100
From:   Alexandre Belloni <alexandre.belloni@...tlin.com>
To:     Tudor.Ambarus@...rochip.com
Cc:     Nicolas.Ferre@...rochip.com, Ludovic.Desroches@...rochip.com,
        robh+dt@...nel.org, mark.rutland@....com,
        Cyrille.Pitchen@...rochip.com,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, boris.brezillon@...tlin.com,
        linux-mtd@...ts.infradead.org, broonie@...nel.org,
        linux-spi@...r.kernel.org
Subject: Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR
 memory nodes

On 11/12/2018 12:32:40+0000, Tudor.Ambarus@...rochip.com wrote:
> Hi, Alexandre,
> 
> On 12/10/2018 11:35 PM, Alexandre Belloni wrote:
> > Hi,
> > 
> > On 10/12/2018 17:15:29+0000, Tudor.Ambarus@...rochip.com wrote:
> >> From: Cyrille Pitchen <cyrille.pitchen@...rochip.com>
> >>
> >> This patch configures the QSPI0 controller pin muxing and declares
> >> a jedec,spi-nor memory.
> >>
> >> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> >> memory which advertises a maximum frequency of 80MHz for Quad IO
> >> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> >> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
> >>
> >> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@...rochip.com>
> >> [tudor.ambarus@...rochip.com:
> >> - drop partitions,
> >> - add spi-rx/tx-bus-width
> >> - change spi-max-frequency to match the 80MHz limit advertised by
> >>   MX25L25673G for Quad IO Fast Read,
> >> - reword commit message and subject.]
> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com>
> >> ---
> >>  arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> >>  1 file changed, 31 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> >> index 518e2b095ccf..171bc82cfbbf 100644
> >> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> >> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> >> @@ -108,6 +108,21 @@
> >>  		};
> >>  
> >>  		apb {
> >> +			qspi0: spi@...20000 {
> >> +				pinctrl-names = "default";
> >> +				pinctrl-0 = <&pinctrl_qspi0_default>;
> >> +				/* status = "okay"; */ /* conflict with sdmmc1 */
> > 
> > Isn't that conflicting then because I think the default is okay.
> qspi0 is disabled in sama5d2.dtsi.
> 

Ok, then maybe that comment is not necessary at all.

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com