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Message-ID: <CAMty3ZBJGgwKCZSeWQmRRjnx3i5z_rV0GASdKLfjq+dSTGSkdw@mail.gmail.com>
Date: Tue, 18 Dec 2018 17:06:38 +0530
From: Jagan Teki <jagan@...rulasolutions.com>
To: Sean Paul <sean@...rly.run>
Cc: Thierry Reding <thierry.reding@...il.com>,
David Airlie <airlied@...ux.ie>,
dri-devel <dri-devel@...ts.freedesktop.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Michael Trimarchi <michael@...rulasolutions.com>,
linux-amarula@...rulasolutions.com
Subject: Re: [PATCH v3 2/2] drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI
LCD panel
On Sat, Dec 15, 2018 at 3:32 AM Sean Paul <sean@...rly.run> wrote:
>
> On Sat, Dec 15, 2018 at 02:11:01AM +0530, Jagan Teki wrote:
> > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
> >
> > Add panel driver for it.
> >
> > Signed-off-by: Jagan Teki <jagan@...rulasolutions.com>
> > ---
> > Changes for v2:
> > - use simple structure for command init
> > - update proper comments on power, reset delay sequnce
> > - fix to use set_display_off in disable function
> > - move mode type to structure
> > - drop refres rate value, let drm compute
> >
> > MAINTAINERS | 6 +
> > drivers/gpu/drm/panel/Kconfig | 9 +
> > drivers/gpu/drm/panel/Makefile | 1 +
> > .../drm/panel/panel-feiyang-fy07024di26a30d.c | 296 ++++++++++++++++++
> > 4 files changed, 312 insertions(+)
> > create mode 100644 drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index d2928a4d2847..e643238855ea 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -4732,6 +4732,12 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
> > S: Maintained
> > F: drivers/gpu/drm/tve200/
> >
> > +DRM DRIVER FOR FEIYANG FY07024DI26A30-D MIPI-DSI LCD PANELS
> > +M: Jagan Teki <jagan@...rulasolutions.com>
> > +S: Maintained
> > +F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> > +F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.txt
> > +
> > DRM DRIVER FOR ILITEK ILI9225 PANELS
> > M: David Lechner <david@...hnology.com>
> > S: Maintained
>
> As I mentioned on IRC, this will be drm-misc maintained with the other panels,
> no need to have a dedicated MAINTAINERS entry. You'll get pulled from
> get_maintainers.pl as a majority commit signer
This I missed it on IRC, sorry will drop.
>
> > diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> > index d93b2ba709bc..cb8ca93550cf 100644
> > --- a/drivers/gpu/drm/panel/Kconfig
> > +++ b/drivers/gpu/drm/panel/Kconfig
> > @@ -38,6 +38,15 @@ config DRM_PANEL_SIMPLE
> > that it can be automatically turned off when the panel goes into a
> > low power state.
> >
> > +config DRM_PANEL_FEIYANG_FY07024DI26A30D
> > + tristate "Feiyang FY07024DI26A30-D MIPI-DSI LCD panel"
> > + depends on OF
> > + depends on DRM_MIPI_DSI
> > + depends on BACKLIGHT_CLASS_DEVICE
> > + help
> > + Say Y if you want to enable support for panels based on the
> > + Feiyang FY07024DI26A30-D MIPI-DSI interface.
> > +
> > config DRM_PANEL_ILITEK_IL9322
> > tristate "Ilitek ILI9322 320x240 QVGA panels"
> > depends on OF && SPI
> > diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> > index 6a9b4cec1891..0fa0ef69e109 100644
> > --- a/drivers/gpu/drm/panel/Makefile
> > +++ b/drivers/gpu/drm/panel/Makefile
> > @@ -2,6 +2,7 @@
> > obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
> > obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
> > obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
> > +obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
> > obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
> > obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o
> > obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
> > diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> > new file mode 100644
> > index 000000000000..4abccbf62c3c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> > @@ -0,0 +1,296 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018 Amarula Solutions
> > + * Author: Jagan Teki <jagan@...rulasolutions.com>
> > + */
> > +
> > +#include <linux/backlight.h>
> > +#include <linux/delay.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/drm_panel.h>
> > +
> > +#define FEIYANG_INIT_CMD_LEN 2
> > +
> > +struct feiyang {
> > + struct drm_panel panel;
> > + struct mipi_dsi_device *dsi;
> > +
> > + struct backlight_device *backlight;
> > + struct regulator *dvdd;
> > + struct regulator *avdd;
> > + struct gpio_desc *reset;
> > +};
> > +
> > +static inline struct feiyang *panel_to_feiyang(struct drm_panel *panel)
> > +{
> > + return container_of(panel, struct feiyang, panel);
> > +}
> > +
> > +struct feiyang_init_cmd {
> > + u8 data[FEIYANG_INIT_CMD_LEN];
> > +};
> > +
> > +static const struct feiyang_init_cmd feiyang_init_cmds[] = {
> > + { .data = { 0x80, 0x58 } },
> > + { .data = { 0x81, 0x47 } },
> > + { .data = { 0x82, 0xD4 } },
> > + { .data = { 0x83, 0x88 } },
> > + { .data = { 0x84, 0xA9 } },
> > + { .data = { 0x85, 0xC3 } },
> > + { .data = { 0x86, 0x82 } },
> > +};
> > +
> > +static int feiyang_prepare(struct drm_panel *panel)
> > +{
> > + struct feiyang *ctx = panel_to_feiyang(panel);
> > + struct mipi_dsi_device *dsi = ctx->dsi;
> > + unsigned int i;
> > + int ret;
> > +
> > + ret = regulator_enable(ctx->dvdd);
> > + if (ret)
> > + return ret;
> > +
> > + /* T1 (dvdd start + dvdd rise) 0 < T1 <= 10ms */
> > + msleep(10);
> > +
> > + ret = regulator_enable(ctx->avdd);
> > + if (ret)
> > + return ret;
> > +
> > + /* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */
> > + msleep(20);
> > +
> > + gpiod_set_value(ctx->reset, 1);
> > + msleep(50);
> > +
> > + gpiod_set_value(ctx->reset, 0);
> > + /* T5 + T6 (avdd rise + video & logic signal rise)
> > + * T5 >= 10ms, 0 < T6 <= 10ms
> > + */
> > + msleep(20);
> > +
> > + gpiod_set_value(ctx->reset, 1);
> > +
> > + /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
> > + msleep(200);
> > +
> > + for (i = 0; i < ARRAY_SIZE(feiyang_init_cmds); i++) {
> > + const struct feiyang_init_cmd *cmd =
> > + &feiyang_init_cmds[i];
> > +
> > + ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
> > + FEIYANG_INIT_CMD_LEN);
> > + if (ret < 0)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int feiyang_enable(struct drm_panel *panel)
> > +{
> > + struct feiyang *ctx = panel_to_feiyang(panel);
> > +
> > + /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
> > + msleep(200);
> > +
> > + mipi_dsi_dcs_set_display_on(ctx->dsi);
> > + backlight_enable(ctx->backlight);
> > +
> > + return 0;
> > +}
> > +
> > +static int feiyang_disable(struct drm_panel *panel)
> > +{
> > + struct feiyang *ctx = panel_to_feiyang(panel);
> > +
> > + backlight_disable(ctx->backlight);
> > + return mipi_dsi_dcs_set_display_off(ctx->dsi);
> > +}
> > +
> > +static int feiyang_unprepare(struct drm_panel *panel)
> > +{
> > + struct feiyang *ctx = panel_to_feiyang(panel);
> > + int ret;
> > +
> > + ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
> > + if (ret < 0)
> > + DRM_DEV_ERROR(panel->dev, "failed to set display off: %d\n",
> > + ret);
> > +
> > + ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
> > + if (ret < 0)
> > + DRM_DEV_ERROR(panel->dev, "failed to enter sleep mode: %d\n",
> > + ret);
> > +
> > + /* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */
> > + msleep(200);
> > +
> > + gpiod_set_value(ctx->reset, 0);
> > +
> > + gpiod_set_value(ctx->reset, 1);
> > +
> > + gpiod_set_value(ctx->reset, 0);
> > +
> > + regulator_disable(ctx->avdd);
> > +
> > + /* T11 (dvdd rise to fall) 0 < T11 <= 10ms */
> > + msleep(10);
> > +
> > + regulator_disable(ctx->dvdd);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct drm_display_mode feiyang_default_mode = {
> > + .clock = 55000,
> > +
> > + .hdisplay = 1024,
> > + .hsync_start = 1024 + 396,
> > + .hsync_end = 1024 + 396 + 20,
> > + .htotal = 1024 + 396 + 20 + 100,
> > +
> > + .vdisplay = 600,
> > + .vsync_start = 600 + 12,
> > + .vsync_end = 600 + 12 + 2,
> > + .vtotal = 600 + 12 + 2 + 21,
>
> These timings are still incorrect, they'll give a 56.2Hz refresh rate. Is that
> really what you want?
I would like to go with same rate as of now since BSP is using the
same, since I don't have any information from chip vendor(even I wrote
it and waiting for response). I will update accordingly once I get the
information from vendor.
Let me know your inputs.
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