linux-kernel - Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <VI1PR04MB5533533242C036C5CF6352BAEEBD0@VI1PR04MB5533.eurprd04.prod.outlook.com>
Date:   Tue, 18 Dec 2018 18:09:02 +0000
From:   Leonard Crestez <leonard.crestez@....com>
To:     Rob Herring <robh@...nel.org>,
        Andrey Smirnov <andrew.smirnov@...il.com>,
        Lucas Stach <l.stach@...gutronix.de>
CC:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Fabio Estevam <fabio.estevam@....com>,
        Chris Healy <cphealy@...il.com>,
        Aisheng Dong <aisheng.dong@....com>,
        Richard Zhu <hongxing.zhu@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        dl-linux-imx <linux-imx@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
Subject: Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ

On 12/18/2018 5:15 PM, Rob Herring wrote:
> On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote:
>> Add code needed to support i.MX8MQ variant.
>>
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
>> Reviewed-by: Lucas Stach <l.stach@...gutronix.de>

>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>>   
>> +Additional required properties for imx8mq-pcie:
>> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
>> +
> 
> Remove this.
> 
> If GPR register offset is what you need, then put that into DT.
> Typically, we'd have a property with iomuxc phandle and offset.

This series initially added explicit offsets but I suggested a single 
"controller-id" because:
  * There are multiple bit and byte offsets
  * Other imx8 SOCs also have 2x pcie with other bit/byte offsets

Hiding this behind a compatible string and single "controller-id" seem 
preferable to elaborating register maps in dt bindings. It also makes 
upgrades simpler: if features are added which use other bits there is no 
need to describe them in DT and deal with compatibility headaches.

Link to older thread: https://lkml.org/lkml/2018/11/29/888

It's possible my suggestion was misguided.