linux-kernel - Re: [PATCH 1/3] pinctrl: armada-37xx: Correct mpp definitions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <87efa6c0tw.fsf@bootlin.com>
Date:   Mon, 24 Dec 2018 18:05:15 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Marek Behun <marek.behun@....cz>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jason Cooper <jason@...edaemon.net>,
        Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        linux-arm-kernel@...ts.infradead.org,
        Antoine Tenart <antoine.tenart@...tlin.com>,
        Miquèl Raynal <miquel.raynal@...tlin.com>,
        Maxime Chevallier <maxime.chevallier@...tlin.com>,
        Nadav Haklai <nadavh@...vell.com>,
        Marcin Wojtas <mw@...ihalf.com>
Subject: Re: [PATCH 1/3] pinctrl: armada-37xx: Correct mpp definitions

Hi Marek,

 On sam., déc. 22 2018, Marek Behun <marek.behun@....cz> wrote:

> On Fri, 21 Dec 2018 18:32:57 +0100
> Gregory CLEMENT <gregory.clement@...tlin.com> wrote:
>
>> +	PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
>> +	PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
>
> If the pair is split to clkreq and reset, shouldn't the first be called
> pcie1_reset?

I considered this but chose to keep pcie1 in order to preserve backward
compatibility.

I agree that it is debatable, because without the fix the old device
tree can't work. However I find it better preserving the initial intent
of an existing device tree.

By talking about it, I think about an other option, keeping pcie1 name
to setup the pins 39 and 40 how it was documented. And introducing
pcie1_reset and pcie1_clkreq for new binding. however I don't know how
it could be handle by the pinctrl framework.

Gregory

> Marek

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com