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Message-ID: <SG2PR04MB3415A7CA56902CA965E6F62FAAB70@SG2PR04MB3415.apcprd04.prod.outlook.com>
Date: Fri, 28 Dec 2018 10:09:40 +0000
From: Huang nut <minhaco@....com>
To: "herbert@...dor.apana.org.au" <herbert@...dor.apana.org.au>,
"davem@...emloft.net" <davem@...emloft.net>
CC: "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Huang nut <minhaco@....com>
Subject: [PATCH] crypto: Fix typo in "pclmul"
From: haco <minhaco@....com>
Fix typo "plcmul" to "pclmul"
Signed-off-by: Huaxuan Mao <minhaco@....com>
---
crypto/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 045af6eeb..bc854c23d 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -642,7 +642,7 @@ config CRYPTO_CRC32_PCLMUL
From Intel Westmere and AMD Bulldozer processor with SSE4.2
and PCLMULQDQ supported, the processor will support
CRC32 PCLMULQDQ implementation using hardware accelerated PCLMULQDQ
- instruction. This option will create 'crc32-plcmul' module,
+ instruction. This option will create 'crc32-pclmul' module,
which will enable any routine to use the CRC-32-IEEE 802.3 checksum
and gain better performance as compared with the table implementation.
@@ -671,7 +671,7 @@ config CRYPTO_CRCT10DIF_PCLMUL
For x86_64 processors with SSE4.2 and PCLMULQDQ supported,
CRC T10 DIF PCLMULQDQ computation can be hardware
accelerated PCLMULQDQ instruction. This option will create
- 'crct10dif-plcmul' module, which is faster when computing the
+ 'crct10dif-pclmul' module, which is faster when computing the
crct10dif checksum as compared with the generic table implementation.
config CRYPTO_CRCT10DIF_VPMSUM
--
2.20.1
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