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Message-ID: <AM6PR0702MB3799A0BC3B07541CDBC4027EFA8A0@AM6PR0702MB3799.eurprd07.prod.outlook.com>
Date: Tue, 8 Jan 2019 08:10:39 +0000
From: "Wiebe, Wladislav (Nokia - DE/Ulm)" <wladislav.wiebe@...ia.com>
To: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"mchehab+samsung@...nel.org" <mchehab+samsung@...nel.org>,
"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
"davem@...emloft.net" <davem@...emloft.net>,
"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
"nicolas.ferre@...rochip.com" <nicolas.ferre@...rochip.com>,
"arnd@...db.de" <arnd@...db.de>,
"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"bp@...en8.de" <bp@...en8.de>,
"mchehab@...nel.org" <mchehab@...nel.org>,
"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
"nicolas.ferre@...rochip.com" <nicolas.ferre@...rochip.com>,
"arnd@...db.de" <arnd@...db.de>,
"Sverdlin, Alexander (Nokia - DE/Ulm)" <alexander.sverdlin@...ia.com>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: [PATCH 1/2] dt-bindings: edac: ARM Cortex A15 L2 asynchronous error
detection
Add property description + example for using the
Cortex A15 L2 asynchronous error detection driver.
Signed-off-by: Wladislav Wiebe <wladislav.wiebe@...ia.com>
---
.../bindings/edac/cortex_a15_l2_async_edac.txt | 22 ++++++++++++++++++++++
MAINTAINERS | 7 +++++++
2 files changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/cortex_a15_l2_async_edac.txt
diff --git a/Documentation/devicetree/bindings/edac/cortex_a15_l2_async_edac.txt b/Documentation/devicetree/bindings/edac/cortex_a15_l2_async_edac.txt
new file mode 100644
index 000000000000..9ad8c2497e70
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/cortex_a15_l2_async_edac.txt
@@ -0,0 +1,22 @@
+* ARM Cortex A15 L2 internal asynchronous error detection driver
+
+Support for L2 internal asynchronous error detection caused by L2 RAM
+double-bit ECC error or illegal writes to the Interrupt Controller
+memory-map region on the Cortex A15.
+
+Required properties:
+ - compatible: "arm,cortex-a15-l2-async-edac"
+ - interrupts: INTERRIRQ per CPU cluster
+
+Example:
+
+cortex-a15-l2-async-edac {
+ compatible = "arm,cortex-a15-l2-async-edac";
+ interrupts = <0 182 4>,
+ <0 183 4>,
+ <0 184 4>,
+ <0 185 4>;
+};
+
+Reference:
+Cortex-A15 Technical Reference Manual, 7.7. Asynchronous errors
diff --git a/MAINTAINERS b/MAINTAINERS
index b755a89fa325..0796ad6e6490 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1094,6 +1094,13 @@ F: arch/arm/include/asm/arch_timer.h
F: arch/arm64/include/asm/arch_timer.h
F: drivers/clocksource/arm_arch_timer.c
+ARM CORTEX A15 L2 INTERNAL ASYNCHRONOUS ERROR DETECTION DRIVER
+M: Wladislav Wiebe <wladislav.wiebe@...ia.com>
+L: linux-edac@...r.kernel.org
+L: linux-arm-kernel@...ts.infradead.org (moderated for non-subscribers)
+S: Supported
+F: Documentation/devicetree/bindings/edac/cortex_a15_l2_async_edac.txt
+
ARM INTEGRATOR, VERSATILE AND REALVIEW SUPPORT
M: Linus Walleij <linus.walleij@...aro.org>
L: linux-arm-kernel@...ts.infradead.org (moderated for non-subscribers)
--
2.16.1
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