linux-kernel - Re: [PATCH] drm/msm: Fix A6XX support for opp-level

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Message-ID: <20190112000206.GB14059@jcrouse-lnx.qualcomm.com>
Date:   Fri, 11 Jan 2019 17:02:06 -0700
From:   Jordan Crouse <jcrouse@...eaurora.org>
To:     Douglas Anderson <dianders@...omium.org>
Cc:     Rob Clark <robdclark@...il.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Andy Gross <andy.gross@...aro.org>,
        linux-arm-msm@...r.kernel.org,
        Viresh Kumar <viresh.kumar@...aro.org>,
        "Kristian H . Kristensen" <hoegsberg@...omium.org>,
        Colin Ian King <colin.king@...onical.com>,
        linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        Sharat Masetty <smasetty@...eaurora.org>,
        David Airlie <airlied@...ux.ie>,
        freedreno@...ts.freedesktop.org,
        Mamta Shukla <mamtashukla555@...il.com>,
        Daniel Vetter <daniel@...ll.ch>
Subject: Re: [PATCH] drm/msm: Fix A6XX support for opp-level

On Fri, Jan 11, 2019 at 02:27:21PM -0800, Douglas Anderson wrote:
> The bindings for Qualcomm opp levels changed after being Acked but
> before landing.  Thus the code in the GPU that was relying on the old
> bindings is now broken.
> 
> While we could just change the string 'qcom,level' to the string
> 'opp-level', it actually seems better to use the newly-introduced
> dev_pm_opp_get_level().
> 
> This patch thus has a hard dependency on the outstanding patch ("OPP:
> Add support for parsing the 'opp-level' property") and will need to
> land in a tree that contains that patch.
> 
> This patch needs to land before the patch ("arm64: dts: sdm845: Add
> gpu and gmu device nodes") since if a tree contains the device tree
> patch but not this one you'll get a crash at bootup.
> 
> Signed-off-by: Douglas Anderson <dianders@...omium.org>

Reviewed-by: Jordan Crouse <jcrouse@...eaurora.org>

> ---
> 
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 17 ++++++-----------
>  1 file changed, 6 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 5beb83d1cf87..900f18dc1577 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -928,25 +928,20 @@ static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
>  }
>  
>  /* Return the 'arc-level' for the given frequency */
> -static u32 a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq)
> +static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
> +					   unsigned long freq)
>  {
>  	struct dev_pm_opp *opp;
> -	struct device_node *np;
> -	u32 val = 0;
> +	unsigned int val;
>  
>  	if (!freq)
>  		return 0;
>  
> -	opp  = dev_pm_opp_find_freq_exact(dev, freq, true);
> +	opp = dev_pm_opp_find_freq_exact(dev, freq, true);
>  	if (IS_ERR(opp))
>  		return 0;
>  
> -	np = dev_pm_opp_get_of_node(opp);
> -
> -	if (np) {
> -		of_property_read_u32(np, "qcom,level", &val);
> -		of_node_put(np);
> -	}
> +	val = dev_pm_opp_get_level(opp);
>  
>  	dev_pm_opp_put(opp);
>  
> @@ -982,7 +977,7 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
>  	/* Construct a vote for each frequency */
>  	for (i = 0; i < freqs_count; i++) {
>  		u8 pindex = 0, sindex = 0;
> -		u32 level = a6xx_gmu_get_arc_level(dev, freqs[i]);
> +		unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
>  
>  		/* Get the primary index that matches the arc level */
>  		for (j = 0; j < pri_count; j++) {
> -- 
> 2.20.1.97.g81188d93c3-goog
> 

-- 
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