[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <BN7PR12MB2836F9781A77332B1C813B04C2810@BN7PR12MB2836.namprd12.prod.outlook.com>
Date: Tue, 15 Jan 2019 20:06:33 +0000
From: Sowjanya Komatineni <skomatineni@...dia.com>
To: Rob Herring <robh@...nel.org>
CC: "mark.rutland@....com" <mark.rutland@....com>,
Mikko Perttunen <mperttunen@...dia.com>,
"chunyan.zhang@...soc.com" <chunyan.zhang@...soc.com>,
"thierry.reding@...il.com" <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
"adrian.hunter@...el.com" <adrian.hunter@...el.com>,
"ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
Aniruddha Tvs Rao <anrao@...dia.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>
Subject: RE: [PATCH V8 1/3] dt-bindings: mmc: tegra: Add supports-cqe property
DKIM-Signature: v. a.a-sha256; c.laxed/relaxed; d.idia.com; s.;
t.47582767; bh�I+2QAF0U3LjTqHgWZ1Gp4eGvtuhVGU38vlx4M4cSI h.PGP-Universal:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:
Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach:
X-MS-TNEF-Correlator:authentication-results:x-originating-ip:
x-ms-publictraffictype:x-microsoft-exchange-diagnostics:
x-ms-exchange-antispam-srfa-diagnostics:
x-forefront-antispam-report:
x-ms-office365-filtering-correlation-id:x-microsoft-antispam:
x-ms-traffictypediagnostic:x-microsoft-antispam-prvs:
x-forefront-prvs:received-spf:x-ms-exchange-senderadcheck:
x-microsoft-antispam-message-info:spamdiagnosticoutput:
spamdiagnosticmetadata:MIME-Version:
X-MS-Exchange-CrossTenant-Network-Message-Id:
X-MS-Exchange-CrossTenant-originalarrivaltime:
X-MS-Exchange-CrossTenant-fromentityheader:
X-MS-Exchange-CrossTenant-id:
X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg:
Content-Language:Content-Type:Content-Transfer-Encoding;
b.I9QoalgPAZF7EC8J1YrU0VjmgUCINkyQW/clat+R0XYz/TLuq9NbuNGpfo0liIX
8VWopR1BJ1noS8vRUL+ZgZFS6b1FDe346K/z3tgV0u/ZPUpSaAunmfKVVy0cLeHg/K
IfxsTc7dQT38saLfI2E1eizM1RKGsmxiE8/ItGgTH54qGmBI/vqKlkqTWXtQ7KoyKC
CQAp+Rxbs9/14Cj42/ouzXYiqTQwDQgKtFqzLjDzH6UAzKEc1jlV4Q4mJyqJAPpyNp
7EyhDGK0abFNJsaP/qsYGxdAoI0+uFHPq/2hCz46T5tP6fZDxntjYZvDmT3J3TVpSI
sFfSIkSnSIKVg
>> Add supports-cqe optional property for Tegra SDMMC.
>>
>> Tegra186 and Tegra194 supports HW Command queue only on SDMMC4
>> controller. This property is used to identify command queue support
>> controller in the tegra sdhci driver.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
>> ---
>> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4
>> ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> index 32b4b4e41923..fb14c2c8d7ee 100644
>> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> @@ -72,6 +72,10 @@ Optional properties for Tegra210 and Tegra186:
>> - nvidia,default-trim : Specify the default outbound clock trimmer
>> value.
>> - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
>> +- supports-cqe : The presence of this property indicates that the
>> + corresponding controller supports HW command queue feature.
>> + Tegra186 and Tegra194 has 4 SDMMC Controllers and only SDMMC4
>> + controller supports HW Command Queue with eMMC device.
>
>Don't SDHCI capability bits do this? If not, this should probably be common.
>
>Rob
Tegra has 4 SDMMC controllers and HW Command queue is supported only on SDMMC4.
There is no bit field specific in SDMMC4 alone to indicate this. So added supports-cqe to
identifying this thru Device tree.
Thanks
Sowjanya
Powered by blists - more mailing lists