linux-kernel - Re: question about head

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Message-ID: <642e4121-229f-7627-7f1d-737eb8ed4e5f@cn.fujitsu.com>
Date:   Wed, 16 Jan 2019 17:44:26 +0800
From:   Cao jin <caoj.fnst@...fujitsu.com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     Ingo Molnar <mingo@...hat.com>, <bp@...en8.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        <kirill.shutemov@...ux.intel.com>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: question about head_64.S

On 1/15/19 11:55 PM, Thomas Gleixner wrote:
> On Tue, 15 Jan 2019, Cao jin wrote:
> 
>> Hi,
>>   I have been digging into this file for a while, and I still have 2
>> questions unclear, hope to get your help.
>>
>> 1.
>> At the entry of startup_64, we set all the data segment registers to 0,
>> according to commit 08da5a2ca("x86_64: Early segment setup for VT"), it
>> is said to accelerate the decompression under VT. I don't know Intel VT,
>> but I did test under physical machine and virtual machine(with KVM, and
>> intel VT enabled in BIOS) with following patch:
>>
>> diff --git a/arch/x86/boot/compressed/head_64.S
>> b/arch/x86/boot/compressed/head_64.S
>> index 58f6a467f1fa..595f3c300173 100644
>> --- a/arch/x86/boot/compressed/head_64.S
>> +++ b/arch/x86/boot/compressed/head_64.S
>> @@ -260,12 +260,12 @@ ENTRY(startup_64)
>>          */
>>
>>         /* Setup data segments. */
>> -       xorl    %eax, %eax
>> -       movl    %eax, %ds
>> -       movl    %eax, %es
>> -       movl    %eax, %ss
>> -       movl    %eax, %fs
>> -       movl    %eax, %gs
>> +//     xorl    %eax, %eax
>> +//     movl    %eax, %ds
>> +//     movl    %eax, %es
>> +//     movl    %eax, %ss
>> +//     movl    %eax, %fs
>> +//     movl    %eax, %gs
>>
>> I don't see any obvious booting time difference, is there anything I missed?
>> Also, I don't find explicit document saying we should zero these
>> registers under VT.
> 
> The decompressor is position independent code, so all segments have to be
> set to 0.
> 

Thank you Thomas! But I've never heard that PIC is correlated with
segment register value, could you elaborate a little bit? Because as I
know, startup_64 is in long mode, and CPU will treat all segment(except
fs, gs) base as 0, no matter whatever in them. And until now, I only see
fs is touched when parsing command line, not see any explicit gs usage.

On the other hand, I test the patch above, it can boot up, so seems
segment register value here is not necessary to be 0?

> The patch you mentioned was just adding fs/gs to the list of segments
> which are cleared and the commit message is not very clear. Though if you
> dig further down then you find the original version of that patch:
> 
>   commit ffb6017563aa("[PATCH] x86-64: x86_64 - Fix FS/GS registers for VT execution")
> 
> That one has a proper explantaion.
> 

Oh, I still not reach to the real kernel itself yet. At first glance,
"but it is important to reload them in protected mode" make sense to me.

But more confusion rise up: under 64-bit boot protocol, we can have more
than one entry? startup_64 in both:

  arch/x86/kernel/head_64.S
and
  arch/x86/boot/compressed/head_64.S

can be jumped to via bootloader? Seems Documentation/x86/boot.txt
doesn't say that.

-- 
Sincerely,
Cao jin