linux-kernel - Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support

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Message-ID: <1384cbbb-6e3e-f2e3-5ea4-8d0b237d64c7@codeaurora.org>
Date:   Fri, 25 Jan 2019 00:01:04 +0530
From:   Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To:     Mathieu Poirier <mathieu.poirier@...aro.org>
Cc:     Suzuki K Poulose <suzuki.poulose@....com>,
        Rob Herring <robh+dt@...nel.org>, Leo Yan <leo.yan@...aro.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Vivek Gautam <vivek.gautam@...eaurora.org>,
        Doug Anderson <dianders@...omium.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        devicetree@...r.kernel.org, Mark Rutland <mark.rutland@....com>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Sibi Sankar <sibis@...eaurora.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        John Horley <john.horley@....com>
Subject: Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support

Good day Mathieu,

On 1/24/2019 9:37 PM, Mathieu Poirier wrote:
> Good day Sai,
> 
> On Wed, 23 Jan 2019 at 13:18, Sai Prakash Ranjan
> <saiprakash.ranjan@...eaurora.org> wrote:
>>
>> Hi Mathieu,
>>
>> On 1/24/2019 12:44 AM, Mathieu Poirier wrote:
>>> On Wed, 23 Jan 2019 at 05:12, Sai Prakash Ranjan
>>> <saiprakash.ranjan@...eaurora.org> wrote:
>>>
>>> That depends on whether the ETMs have been modified at all, something
>>> Suzuki has asked to be clarified.  If ETMs have been modified then we
>>> need to understand how they differ from the driver's implementation.
>>
>> We had asked hardware team for clarification regarding this. Let me
>> poke them again. As for the driver, downstream implementation also
>> uses the same driver, so I am not sure what do you mean by differing
>> from the driver's implementation.
> 
> The driver has been implemented in accordance to ARM's coresight
> technical reference manual and expects the HW to behave in accordance
> to that specification.  Here we want to make sure the IP on your board
> is conformant to the same specification.  If not then the driver needs
> to be made flexible to handle both kind IPs.
> 

The HW does behave as per the specification. As discussed in reply to
Suzuki, Coresight peripherals do use JEP106 ID of ARM for SDM845 and for 
MSM8996, the ID is of QCOM(0x70) since it was not based on any ARM 
derivative.
And the etm4x driver handles it all well. Other values of PID registers
are implementation defined and can be different from standard ARM cpu
core types.

Thanks,
Sai

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