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Message-ID: <20190129151916.GA12635@ravnborg.org>
Date:   Tue, 29 Jan 2019 16:19:16 +0100
From:   Sam Ravnborg <sam@...nborg.org>
To:     Jagan Teki <jagan@...rulasolutions.com>
Cc:     Thierry Reding <thierry.reding@...il.com>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        Michael Trimarchi <michael@...rulasolutions.com>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-amarula@...rulasolutions.com
Subject: Re: [PATCH v5 2/2] drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI
 LCD panel

Hi Jagan.

> >
> > I see DRM_MODE_ARG as mode argument, that print all mode timings but
> > here we need only 3 timings out of it. do we really need? if yes
> > please suggest an example.
> 
> fyi: sent v6 for this except this change. Let me know if you have any
> comments on this.

Drivers looks fine, the above was just a quick suggestion to use some
exising plumbing.

You have done a nice job following up on all the feedback.

	Sam

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