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Message-ID: <154887625299.169292.6293540451460425008@swboyd.mtv.corp.google.com>
Date: Wed, 30 Jan 2019 11:24:12 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Andy Gross <andy.gross@...aro.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
David Brown <david.brown@...aro.org>,
Khasim Syed Mohammed <khasim.mohammed@...aro.org>,
Kishon Vijay Abraham I <kishon@...com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Mark Rutland <mark.rutland@....com>,
Michael Turquette <mturquette@...libre.com>,
Niklas Cassel <niklas.cassel@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Stanimir Varbanov <svarbanov@...sol.com>,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org
Subject: Re: [PATCH 7/7] arm64: dts: qcom: qcs404: Add PCIe related nodes
Quoting Bjorn Andersson (2019-01-25 15:45:09)
> @@ -771,6 +788,56 @@
> status = "disabled";
> };
> };
> +
> + pcie: pci@...00000 {
> + compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
> + reg = <0x10000000 0xf1d
Nitpick: Can you format these like <0x10000000 0xf1d>, <0x10000f20 0xa8>, etc?
> + 0x10000f20 0xa8
> + 0x07780000 0x2000
> + 0x10001000 0x2000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */
Same for this one? It's nice to know what the size of the cells are.
> + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
> +
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