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Message-Id: <20190125234509.26419-2-bjorn.andersson@linaro.org>
Date: Fri, 25 Jan 2019 15:45:03 -0800
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: Andy Gross <andy.gross@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
David Brown <david.brown@...aro.org>,
Khasim Syed Mohammed <khasim.mohammed@...aro.org>,
Kishon Vijay Abraham I <kishon@...com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Mark Rutland <mark.rutland@....com>,
Niklas Cassel <niklas.cassel@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Stanimir Varbanov <svarbanov@...sol.com>,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org
Subject: [PATCH 1/7] clk: gcc-qcs404: Add PCIe resets
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
---
Stephen, I suggest that we merge this patch through Andy's devicetree branch,
together with the DT patch in the end of this series.
drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 64da032bb9ed..cfb8789ff706 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = {0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = {0x3e040, 5},
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = {0x3e040, 4},
+ [GCC_PCIE_0_AXI_MASTER_ARES] = {0x3e040, 3},
+ [GCC_PCIE_0_CORE_STICKY_ARES] = {0x3e040, 2},
+ [GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1},
+ [GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0},
[GCC_EMAC_BCR] = { 0x4e000 },
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 6ceb55ed72c6..00ab0d77b38a 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -161,5 +161,12 @@
#define GCC_PCIE_0_LINK_DOWN_BCR 11
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
+#define GCC_PCIE_0_AHB_ARES 15
+#define GCC_PCIE_0_AXI_SLAVE_ARES 16
+#define GCC_PCIE_0_AXI_MASTER_ARES 17
+#define GCC_PCIE_0_CORE_STICKY_ARES 18
+#define GCC_PCIE_0_SLEEP_ARES 19
+#define GCC_PCIE_0_PIPE_ARES 20
#endif
--
2.18.0
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