linux-kernel - Re: [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi controller

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Message-ID: <8b935a95-0aaa-3430-e2c2-f5793fd9cf11@microchip.com>
Date:   Fri, 1 Feb 2019 14:49:27 +0000
From:   <Tudor.Ambarus@...rochip.com>
To:     <bbrezillon@...nel.org>
CC:     <mark.rutland@....com>, <devicetree@...r.kernel.org>,
        <alexandre.belloni@...tlin.com>, <linux-kernel@...r.kernel.org>,
        <robh+dt@...nel.org>, <linux-spi@...r.kernel.org>,
        <Ludovic.Desroches@...rochip.com>, <broonie@...nel.org>,
        <linux-mtd@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi
 controller



On 02/01/2019 09:57 AM, Boris Brezillon wrote:
> On Fri, 1 Feb 2019 07:07:40 +0000
> <Tudor.Ambarus@...rochip.com> wrote:
> 
>>>   
>>>>  #define QSPI_IFR_TFRTYP_MASK            GENMASK(13, 12)
>>>>  #define QSPI_IFR_TFRTYP_TRSFR_READ      (0 << 12)
>>>>  #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM  (1 << 12)  
>>>
>>> Looks like the read/write flag is on bit 13. Can we just add  
>>
>> for sama5d2 only
> 
> Feel free to prefix macros with the SoC name to make it clear:
> 
> #define QSPI_IFR_SAMA5D2_WRITE_TRSFR		BIT(13)

agreed

> 

cut

>>>> +#define QSPI_IFR_APBTFRTYP_READ		BIT(24)
> 
> And this one would be
> 
> define QSPI_IFR_SAM9X60_READ_TRSFR		BIT(24)

I prefer letting this bit named as in the datasheet, QSPI_IFR_APBTFRTYP_READ,
and change it if future versions of the IP will modify its sense. It is a READ
transfer done on APB, it is more generic this way. If you have a strong opinion
on this, please let me know.

ta