[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20190211074141.GA49295@gmail.com>
Date: Mon, 11 Feb 2019 08:41:41 +0100
From: Ingo Molnar <mingo@...nel.org>
To: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, x86@...nel.org,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
stable@...r.kernel.org
Subject: Re: [PATCH v2] PCI: Fixup the RTIT_BAR of Intel TH on Denverton
* Alexander Shishkin <alexander.shishkin@...ux.intel.com> wrote:
> On Denverton's integration of the Intel(R) Trace Hub (for a reference
> and overview see Documentation/trace/intel_th.txt) the reported size of
> one of its resources (RTIT_BAR) doesn't match its actual size, which
> leads to overlaps with other devices' resources.
Note that in the latest kernels it's Documentation/trace/intel_th.rst,
not .txt.
Thanks,
Ingo
Powered by blists - more mailing lists