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Date: Tue, 12 Feb 2019 23:17:13 -0800 From: Bjorn Andersson <bjorn.andersson@...aro.org> To: Taniya Das <tdas@...eaurora.org> Cc: Stephen Boyd <sboyd@...nel.org>, Michael Turquette <mturquette@...libre.com>, Andy Gross <andy.gross@...aro.org>, David Brown <david.brown@...aro.org>, Rajendra Nayak <rnayak@...eaurora.org>, linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v1] clk: qcom: lpass: Add CLK_IGNORE_UNUSED for lpass clocks On Thu 20 Dec 03:46 PST 2018, Taniya Das wrote: > The LPASS clocks has a dependency on the GCC lpass clocks to be enabled > before accessing them and that was the reason to mark the gcc lpass clocks > as critical. I have the same problem with the TuringCC in QCS404, that in order to disable the unused clocks GCC_CDSP_CFG_AHB_CLK must be on. But rather than marking either side as critical or ignore-unused I think a better solution is to describe this dependency by using the fact that the clock framework wraps any accesses in pm_runtime_get()/put() calls. So we can use this to link the clock controller to some resources that needs to be turned on whenever we communicate with it. > But in the case where the lpass subsystem would require a > restart, toggling the lpass reset would from HW clear the SW enable bits > of the GCC lpass clocks. Thus the next time bringing up the lpass subsystem > out of reset would fail. Are you saying that when we toggle AOSS_CC_LPASS_RESTART the enable bit is cleared on all these clocks and we might get out of sync between the clock framework and the hardware? Can you please elaborate a little bit on this? Afaict in the remoteproc driver at least, we first disable the clock then we issue the reset. Regards, Bjorn > > Allow the lpass clock driver to enable/disable the gcc lpass clocks and > mark the lpass clocks not be accessed during late_init if no client vote. > > Signed-off-by: Taniya Das <tdas@...eaurora.org> > --- > drivers/clk/qcom/gcc-sdm845.c | 2 -- > drivers/clk/qcom/lpasscc-sdm845.c | 5 +++++ > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c > index c782e62..8365c97 100644 > --- a/drivers/clk/qcom/gcc-sdm845.c > +++ b/drivers/clk/qcom/gcc-sdm845.c > @@ -3163,7 +3163,6 @@ enum { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "gcc_lpass_q6_axi_clk", > - .flags = CLK_IS_CRITICAL, > .ops = &clk_branch2_ops, > }, > }, > @@ -3177,7 +3176,6 @@ enum { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "gcc_lpass_sway_clk", > - .flags = CLK_IS_CRITICAL, > .ops = &clk_branch2_ops, > }, > }, > diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c > index e246b99..1acc741 100644 > --- a/drivers/clk/qcom/lpasscc-sdm845.c > +++ b/drivers/clk/qcom/lpasscc-sdm845.c > @@ -22,6 +22,7 @@ > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "lpass_q6ss_ahbm_aon_clk", > + .flags = CLK_IGNORE_UNUSED, > .ops = &clk_branch2_ops, > }, > }, > @@ -35,6 +36,7 @@ > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "lpass_q6ss_ahbs_aon_clk", > + .flags = CLK_IGNORE_UNUSED, > .ops = &clk_branch2_ops, > }, > }, > @@ -49,6 +51,7 @@ > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "lpass_qdsp6ss_core_clk", > + .flags = CLK_IGNORE_UNUSED, > .ops = &clk_branch2_ops, > }, > }, > @@ -63,6 +66,7 @@ > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "lpass_qdsp6ss_xo_clk", > + .flags = CLK_IGNORE_UNUSED, > .ops = &clk_branch2_ops, > }, > }, > @@ -77,6 +81,7 @@ > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "lpass_qdsp6ss_sleep_clk", > + .flags = CLK_IGNORE_UNUSED, > .ops = &clk_branch2_ops, > }, > }, > -- > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member > of the Code Aurora Forum, hosted by the Linux Foundation. >
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