linux-kernel - Re: [RESEND PATCH v4,2/3] arm64: dts: Using standard CCF interface to set vcodec clk

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Thu, 14 Feb 2019 13:21:41 +0100
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Yunfei Dong <yunfei.dong@...iatek.com>,
        Hans Verkuil <hverkuil@...all.nl>,
        Tiffany Lin <tiffany.lin@...iatek.com>,
        Andrew-CT Chen <andrew-ct.chen@...iatek.com>,
        Rob Herring <robh+dt@...nel.org>
Cc:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-media@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        Qianqian Yan <qianqian.yan@...iatek.com>
Subject: Re: [RESEND PATCH v4,2/3] arm64: dts: Using standard CCF interface to
 set vcodec clk



On 14/02/2019 03:24, Yunfei Dong wrote:
> Using standard CCF interface to set vdec/venc parent clk
> and clk rate.
> 
> Signed-off-by: Yunfei Dong <yunfei.dong@...iatek.com>
> Signed-off-by: Qianqian Yan <qianqian.yan@...iatek.com>
> ---

now pushed to v5.1-next/dts64

Thanks,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8173.dtsi |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 412ffd4..126d11e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1305,6 +1305,15 @@
>  				      "vencpll",
>  				      "venc_lt_sel",
>  				      "vdec_bus_clk_src";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
> +					  <&topckgen CLK_TOP_CCI400_SEL>,
> +					  <&topckgen CLK_TOP_VDEC_SEL>,
> +					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
> +					  <&apmixedsys CLK_APMIXED_VENCPLL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D2>,
> +						 <&topckgen CLK_TOP_VCODECPLL>;
> +			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
>  		};
>  
>  		larb1: larb@...10000 {
> @@ -1370,6 +1379,10 @@
>  				      "venc_sel",
>  				      "venc_lt_sel_src",
>  				      "venc_lt_sel";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> +					  <&topckgen CLK_TOP_VENC_LT_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
> +						 <&topckgen CLK_TOP_UNIVPLL1_D2>;
>  		};
>  
>  		vencltsys: clock-controller@...00000 {
>