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Message-ID: <3f77d34a-a2a4-a2c1-a4e6-32669ff69357@xs4all.nl>
Date: Thu, 14 Feb 2019 08:33:32 +0100
From: Hans Verkuil <hverkuil@...all.nl>
To: Yunfei Dong <yunfei.dong@...iatek.com>,
Tiffany Lin <tiffany.lin@...iatek.com>,
Andrew-CT Chen <andrew-ct.chen@...iatek.com>,
Rob Herring <robh+dt@...nel.org>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Qianqian Yan <qianqian.yan@...iatek.com>
Subject: Re: [RESEND PATCH v4,1/3] media: dt-bindings: media: add
'assigned-clocks' to vcodec examples
Hi Yunfei Dong,
Why is this series resent? Patches 1 and 3 have been merged in our
media master tree already.
Regards,
Hans
On 2/14/19 3:24 AM, Yunfei Dong wrote:
> Fix MTK binding document for MT8173 dtsi changed in order
> to use standard CCF interface.
> MT8173 SoC from Mediatek.
>
> Signed-off-by: Yunfei Dong <yunfei.dong@...iatek.com>
> Signed-off-by: Qianqian Yan <qianqian.yan@...iatek.com>
> Reviewed-by: Rob Herring <robh@...nel.org>
> ---
> .../devicetree/bindings/media/mediatek-vcodec.txt | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> index 2a615d8..b6b5dde 100644
> --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> @@ -66,6 +66,15 @@ vcodec_dec: vcodec@...00000 {
> "vencpll",
> "venc_lt_sel",
> "vdec_bus_clk_src";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
> + <&topckgen CLK_TOP_CCI400_SEL>,
> + <&topckgen CLK_TOP_VDEC_SEL>,
> + <&apmixedsys CLK_APMIXED_VCODECPLL>,
> + <&apmixedsys CLK_APMIXED_VENCPLL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
> + <&topckgen CLK_TOP_UNIVPLL_D2>,
> + <&topckgen CLK_TOP_VCODECPLL>;
> + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
> };
>
> vcodec_enc: vcodec@...02000 {
> @@ -105,4 +114,8 @@ vcodec_dec: vcodec@...00000 {
> "venc_sel",
> "venc_lt_sel_src",
> "venc_lt_sel";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
> + <&topckgen CLK_TOP_UNIVPLL1_D2>;
> };
>
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