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Message-ID: <1550254032-16451-3-git-send-email-abel.vesa@nxp.com>
Date: Fri, 15 Feb 2019 18:07:23 +0000
From: Abel Vesa <abel.vesa@....com>
To: Rob Herring <robh@...nel.org>, Mark Rutland <mark.rutland@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <kernel@...gutronix.de>,
Lucas Stach <l.stach@...gutronix.de>,
Angus Ainslie <angus.ainslie@...i.sm>
CC: Fabio Estevam <fabio.estevam@....com>,
Anson Huang <anson.huang@....com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
dl-linux-imx <linux-imx@....com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Abel Vesa <abel.vesa@....com>
Subject: [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator
According to the schematics, this is a MP2147 switch converter
which is controlled by GPIO1_IO13. When set the gpio is set to
high the regulator output is set to 0.9V. When the gpio is set
to low the regulator output is set to 1V.
Signed-off-by: Abel Vesa <abel.vesa@....com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 36 ++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 54737bf..e5da3dd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -31,6 +31,35 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ buck2_reg: buck2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_buck2>;
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ states = <1000000 0x0
+ 900000 0x1>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
};
&fec1 {
@@ -203,6 +232,13 @@
};
&iomuxc {
+ pinctrl_buck2: vddarmgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
+ >;
+
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
--
2.7.4
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