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Message-ID: <286AC319A985734F985F78AFA26841F73DF71ED6@shsmsx102.ccr.corp.intel.com>
Date:   Fri, 15 Feb 2019 08:56:02 +0000
From:   "Wang, Wei W" <wei.w.wang@...el.com>
To:     'Andi Kleen' <ak@...ux.intel.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "Liang, Kan" <kan.liang@...el.com>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "rkrcmar@...hat.com" <rkrcmar@...hat.com>,
        "Xu, Like" <like.xu@...el.com>,
        "jannh@...gle.com" <jannh@...gle.com>,
        "arei.gonglei@...wei.com" <arei.gonglei@...wei.com>,
        "jmattson@...gle.com" <jmattson@...gle.com>
Subject: RE: [PATCH v5 12/12] KVM/VMX/vPMU: support to report
 GLOBAL_STATUS_LBRS_FROZEN

On Friday, February 15, 2019 12:32 AM, Andi Kleen wrote:
> 
> > +static void intel_pmu_get_global_status(struct kvm_pmu *pmu,
> > +					struct msr_data *msr_info)
> > +{
> > +	u64 guest_debugctl, freeze_lbr_bits =
> DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |
> > +					      DEBUGCTLMSR_LBR;
> > +
> > +	if (!pmu->global_status) {
> > +		msr_info->data = 0;
> > +		return;
> > +	}
> > +
> > +	msr_info->data = pmu->global_status;
> > +	if (pmu->version >= 4) {
> > +		guest_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
> > +		if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits)
> 
> It should only check for the freeze bit, the freeze bit can be set even when
> LBRs are disabled.
> 
> Also you seem to set the bit unconditionally?
> That doesn't seem right. It should only be set after an overflow.
> 
> So the PMI injection needs to set it.

OK. The freeze bits need to be cleared by IA32_PERF_GLOBAL_STATUS_RESET, which seems not supported by the perf code yet (thus guest won't clear them). Would handle_irq_v4 also need to be changed to support that?

Best,
Wei

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