linux-kernel - Re: [RFC 5/5] arm64: dts: imx8mq: Add the opp table and the cpu-supply nodes

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Message-ID: <20190215085624.dtc5uyxch72l2q6g@fsr-ub1664-175>
Date:   Fri, 15 Feb 2019 08:56:25 +0000
From:   Abel Vesa <abel.vesa@....com>
To:     Angus Ainslie <angus@...ea.ca>
CC:     Rob Herring <robh@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Mike Turquette <mturquette@...libre.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Lucas Stach <l.stach@...gutronix.de>,
        Angus Ainslie <angus.ainslie@...i.sm>,
        Anson Huang <anson.huang@....com>,
        dl-linux-imx <linux-imx@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel-owner@...r.kernel.org" 
        <linux-kernel-owner@...r.kernel.org>
Subject: Re: [RFC 5/5] arm64: dts: imx8mq: Add the opp table and the
  cpu-supply nodes

On 19-02-14 16:55:22, Angus Ainslie wrote:
> On 2019-02-13 11:05, Abel Vesa wrote:
> > Add the opp table containing only non over drive opps.
> > Also add the cpu-supply nodes for the A53 cores in the EVK board.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@....com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 +++++++++++++++++
> >  arch/arm64/boot/dts/freescale/imx8mq.dtsi    | 23
> > +++++++++++++++++++++++
> >  2 files changed, 40 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > index 54737bf..114359e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > @@ -31,6 +31,23 @@
> >  		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> >  		enable-active-high;
> >  	};
> > +
> > +};
> > +
> > +&A53_0 {
> > +	cpu-supply = <&sw1a_reg>;
> > +};
> > +
> > +&A53_1 {
> > +	cpu-supply = <&sw1a_reg>;
> > +};
> > +
> > +&A53_2 {
> > +	cpu-supply = <&sw1a_reg>;
> > +};
> > +
> > +&A53_3 {
> > +	cpu-supply = <&sw1a_reg>;
> >  };
> > 
> >  &fec1 {
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 1a89062..89b2d5f 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -91,6 +91,7 @@
> >  			clocks = <&clk IMX8MQ_CLK_ARM>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A53_L2>;
> > +			operating-points-v2 = <&a53_0_opp_table>;
> >  		};
> > 
> >  		A53_1: cpu@1 {
> > @@ -101,6 +102,7 @@
> >  			clocks = <&clk IMX8MQ_CLK_ARM>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A53_L2>;
> > +			operating-points-v2 = <&a53_0_opp_table>;
> >  		};
> > 
> >  		A53_2: cpu@2 {
> > @@ -111,6 +113,7 @@
> >  			clocks = <&clk IMX8MQ_CLK_ARM>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A53_L2>;
> > +			operating-points-v2 = <&a53_0_opp_table>;
> >  		};
> > 
> >  		A53_3: cpu@3 {
> > @@ -121,6 +124,7 @@
> >  			clocks = <&clk IMX8MQ_CLK_ARM>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A53_L2>;
> > +			operating-points-v2 = <&a53_0_opp_table>;
> >  		};
> > 
> >  		A53_L2: l2-cache0 {
> > @@ -666,6 +670,25 @@
> >  			status = "disabled";
> >  		};
> > 
> > +
> > +		a53_0_opp_table: opp-table {
> > +			compatible = "operating-points-v2";
> > +			opp-shared;
> > +
> > +			opp-800000000 {
> > +				opp-hz = /bits/ 64 <800000000>;
> > +				opp-microvolt = <900000>;
> > +				clock-latency-ns = <150000>;
> > +			};
> > +
> > +			opp-1000000000 {
> > +				opp-hz = /bits/ 64 <1000000000>;
> > +				opp-microvolt = <900000>;
> 
> Shouldn't this be
> 
> opp-microvolt = <1000000>;
> 

Hmm, I looked into some older datasheet which said the maximum non
overdrive is 1GHz.

But the latest one I could find:

https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf

says it's 0.8GHz. 

So I'll fix it in the next version.

Thanks.

> > +				clock-latency-ns = <150000>;
> > +				opp-suspend;
> > +			};
> > +		};
> > +
> >  		gic: interrupt-controller@...00000 {
> >  			compatible = "arm,gic-v3";
> >  			reg = <0x38800000 0x10000>,	/* GIC Dist */
>