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Message-Id: <20190216001920.178053-1-rajatja@google.com>
Date: Fri, 15 Feb 2019 16:19:20 -0800
From: Rajat Jain <rajatja@...gle.com>
To: Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
Vishwanath Somayaji <vishwanath.somayaji@...el.com>,
Darren Hart <dvhart@...radead.org>,
Andy Shevchenko <andy@...radead.org>,
platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: rajatxjain@...il.com, Rajat Jain <rajatja@...gle.com>
Subject: [PATCH] platform/x86: intel_pmc_core: Avoid a u32 overflow
The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register.
The pmc_core_adjust_slp_s0_step() could overflow the u32 value while
returning it after adjusting the step. Thus change to u64, this is
already accounted for in debugfs attribute (that wants to output a
64 bit value).
Signed-off-by: Rajat Jain <rajatja@...gle.com>
---
drivers/platform/x86/intel_pmc_core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 22dbf115782e..f90f4dd25151 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -328,9 +328,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
writel(val, pmcdev->regbase + reg_offset);
}
-static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
+static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
{
- return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
+ return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
}
static int pmc_core_dev_state_get(void *data, u64 *val)
--
2.21.0.rc0.258.g878e2cd30e-goog
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