linux-kernel - Re: [PATCH v6 16/22] memory: mtk-smi: Add bus

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Message-ID: <CAE=gft4A=MEYUwwgj4RCT=8Vz_qxbmPo8uG3Mf-HJwC0Zn0-9g@mail.gmail.com>
Date:   Tue, 19 Feb 2019 15:31:35 -0800
From:   Evan Green <evgreen@...omium.org>
To:     Yong Wu <yong.wu@...iatek.com>
Cc:     Joerg Roedel <joro@...tes.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Robin Murphy <robin.murphy@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Tomasz Figa <tfiga@...gle.com>,
        Will Deacon <will.deacon@....com>,
        linux-mediatek@...ts.infradead.org, srv_heupstream@...iatek.com,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
        linux-arm-kernel@...ts.infradead.org,
        iommu@...ts.linux-foundation.org, yingjoe.chen@...iatek.com,
        youlin.pei@...iatek.com, Nicolas Boichat <drinkcat@...omium.org>,
        anan.sun@...iatek.com, Matthias Kaehlcke <mka@...omium.org>
Subject: Re: [PATCH v6 16/22] memory: mtk-smi: Add bus_sel for mt8183

On Sun, Feb 17, 2019 at 1:09 AM Yong Wu <yong.wu@...iatek.com> wrote:
>
> There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
> mmu0 or mmu1 to balance the bandwidth via the smi-common register
> SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
>
> In mt8183, For better performance, we switch larb1/2/5/7 to enter
> mmu1 while the others still keep enter mmu0.
>
> In mt8173 and mt2712, we don't get the performance issue,
> Keep its default value(0x0), that means all the larbs enter mmu0.
>
> Note: smi gen1(mt2701/mt7623) don't have this bus_sel.
>
> And, the base of smi-common is completely different with smi_ao_base
> of gen1, thus I add new variable for that.
>
> CC: Matthias Brugger <matthias.bgg@...il.com>
> Signed-off-by: Yong Wu <yong.wu@...iatek.com>

Reviewed-by: Evan Green <evgreen@...omium.org>