linux-kernel - Re: [PATCH v7] PCI: imx6: limit DBI register length

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Message-ID: <1551113572.3075.172.camel@impinj.com>
Date:   Mon, 25 Feb 2019 16:52:52 +0000
From:   Trent Piepho <tpiepho@...inj.com>
To:     "stefan@...er.ch" <stefan@...er.ch>,
        "leonard.crestez@....com" <leonard.crestez@....com>
CC:     "hongxing.zhu@....com" <hongxing.zhu@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "jingoohan1@...il.com" <jingoohan1@...il.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "gustavo.pimentel@...opsys.com" <gustavo.pimentel@...opsys.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>
Subject: Re: [PATCH v7] PCI: imx6: limit DBI register length

On Mon, 2019-02-25 at 16:15 +0000, Leonard Crestez wrote:
> On Mon, 2019-02-25 at 17:02 +0100, Stefan Agner wrote:
> > Define the length of the DBI registers and limit config space to its
> > length. This makes sure that the kernel does not access registers
> > beyond that point, avoiding the following abort on a i.MX 6Quad:
> > 
> > +static void imx6_pcie_quirk(struct pci_dev *dev)
> > +{
> > +	struct pci_bus *bus = dev->bus;
> > +	struct pcie_port *pp = bus->sysdata;
> > +
> > +	if (bus->number == pp->root_bus_nr) {
> > +		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > +		struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> > +
> > +		/*
> > +		 * Limit config length to avoid the kernel reading beyond
> > +		 * the register set and causing an abort on i.MX 6Quad
> > +		 */
> > +		if (imx6_pcie->drvdata->dbi_length)
> > +			dev->cfg_size = imx6_pcie->drvdata->dbi_length;
> > +	}
> > +}
> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, imx6_pcie_quirk);
> 
> This looks like a default from SYNOPSYS so it likely run on other SOCs
> using the DesignWare PCI IP and crash because of those unchecked casts.

Yes, it's used on IMX7d too.  But it's worse than that, there's a USB
controller core that uses the same vendor and device id,
PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3.  The quirk for that one uses class ==
PCI_CLASS_SERIAL_USB_DEVICE to avoid matching this PCI-e IP.  See
thread "PCI: Check for USB xHCI class for HAPS platform"