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Message-Id: <1551121006-4657-3-git-send-email-thor.thayer@linux.intel.com>
Date: Mon, 25 Feb 2019 12:56:46 -0600
From: thor.thayer@...ux.intel.com
To: bp@...en8.de, dinguyen@...nel.org, linux@...linux.org.uk,
mchehab@...nel.org, james.morse@....com
Cc: thor.thayer@...ux.intel.com, linux-edac@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCHv2 2/2] ARM: socfpga_defconfig: enable EDAC by default
From: Thor Thayer <thor.thayer@...ux.intel.com>
Enable the different ECC blocks by default on Cyclone5
and Arria10.
Signed-off-by: Thor Thayer <thor.thayer@...ux.intel.com>
---
v2 Rebase patch to the arm/defconfig on the arm-soc tree
---
arch/arm/configs/socfpga_defconfig | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 08d1b3e11d68..1f2056c76ef1 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -122,11 +122,23 @@ CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ALTERA=y
+CONFIG_EDAC_ALTERA_SDRAM=y
+CONFIG_EDAC_ALTERA_L2C=y
+CONFIG_EDAC_ALTERA_OCRAM=y
+CONFIG_EDAC_ALTERA_ETHERNET=y
+CONFIG_EDAC_ALTERA_NAND=y
+CONFIG_EDAC_ALTERA_DMA=y
+CONFIG_EDAC_ALTERA_USB=y
+CONFIG_EDAC_ALTERA_QSPI=y
+CONFIG_EDAC_ALTERA_SDMMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
CONFIG_DMATEST=m
+CONFIG_RAS=y
CONFIG_FPGA=y
CONFIG_FPGA_MGR_SOCFPGA=y
CONFIG_FPGA_MGR_SOCFPGA_A10=y
--
2.7.4
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