linux-kernel - Re: [PATCH 1/2] arm64: dts: bitmain: Add GPIO support for BM1880 SoC

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Date:   Thu, 7 Mar 2019 22:54:26 +0530
From:   Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To:     linux-arm-kernel@...ts.infradead.org, linus.walleij@...aro.org
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        haitao.suo@...main.com, darren.tsao@...main.com,
        amit.kucheria@...aro.org, linux-gpio@...r.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: bitmain: Add GPIO support for BM1880 SoC

On Tue, Feb 26, 2019 at 05:20:21PM +0530, Manivannan Sadhasivam wrote:
> Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
> controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.
> 

Applied for v5.2 with Linus's Reviewed-by tag.

Thanks,
Mani

> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
>  arch/arm64/boot/dts/bitmain/bm1880.dtsi | 54 +++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
> index 55a4769e0de2..e4da4ec6a5ee 100644
> --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
> +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
> @@ -80,6 +80,60 @@
>  			#interrupt-cells = <3>;
>  		};
>  
> +		gpio0: gpio@...27000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x0 0x50027000 0x0 0x400>;
> +
> +			porta: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				snps,nr-gpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio1: gpio@...27400 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x0 0x50027400 0x0 0x400>;
> +
> +			portb: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				snps,nr-gpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio2: gpio@...27800 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x0 0x50027800 0x0 0x400>;
> +
> +			portc: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				snps,nr-gpios = <8>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		uart0: serial@...18000 {
>  			compatible = "snps,dw-apb-uart";
>  			reg = <0x0 0x58018000 0x0 0x2000>;
> -- 
> 2.17.1
>