linux-kernel - Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset

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Message-ID: <20190314154627.7f322sd2sd7asnnc@flea>
Date:   Thu, 14 Mar 2019 16:46:28 +0100
From:   Maxime Ripard <maxime.ripard@...tlin.com>
To:     Icenowy Zheng <icenowy@...c.io>
Cc:     Chen-Yu Tsai <wens@...e.org>, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset

On Thu, Mar 14, 2019 at 07:21:08PM +0800, Icenowy Zheng wrote:
> The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
> 
> Fix this problem.
> 
> Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
> Signed-off-by: Icenowy Zheng <icenowy@...c.io>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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