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Date: Tue, 19 Mar 2019 10:34:03 +0100
From: Maxime Jourdan <mjourdan@...libre.com>
To: Jerome Brunet <jbrunet@...libre.com>
Cc: Neil Armstrong <narmstrong@...libre.com>,
linux-clk@...r.kernel.org, linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] clk: meson-g12a: add video decoder clocks
Hi Jerome,
On Tue, Mar 19, 2019 at 10:09 AM Jerome Brunet <jbrunet@...libre.com> wrote:
>
> On Tue, 2019-03-19 at 09:50 +0100, Maxime Jourdan wrote:
>
> A complete sentence would have been nice ;)
>
> Add the video decoder clocks which are ...
>
Sorry about that, I'll apply myself in the future.
> > Mostly like meson-gx, except that the VDEC_HEVC clock is now split in two:
> > HEVC and HEVCF.
> >
> > Signed-off-by: Maxime Jourdan <mjourdan@...libre.com>
> > ---
> > drivers/clk/meson/g12a.c | 160 +++++++++++++++++++++++++++++++++++++++
> > drivers/clk/meson/g12a.h | 8 +-
> > 2 files changed, 167 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> > index 3a3134976534..cfb91df884cb 100644
> > --- a/drivers/clk/meson/g12a.c
> > +++ b/drivers/clk/meson/g12a.c
> > @@ -1495,6 +1495,148 @@ static struct clk_regmap g12a_vpu = {
> > },
> > };
> >
> > +/* VDEC clocks */
> > +
> > +static const char * const g12a_vdec_parent_names[] = {
> > + "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
> > + "hifi_pll", "gp0_pll",
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = HHI_VDEC_CLK_CNTL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_names = g12a_vdec_parent_names,
> > + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_VDEC_CLK_CNTL,
> > + .shift = 0,
> > + .width = 7,
>
> Maxime, the parent mux has "ROUND_CLOSEST" but this div does not, which means
> it will round down. Is it on purpose ?
>
> * If you can't the allow vdec_1 to round above the request (for safety reason
> maybe) then none of the element should round closest.
> * If you want closest achievable frequency (even if higher) for vdec_1, then
> both element should round closest.
>
> Same comment applies below
>
> This is not a blocker but I'd like you to clarify.
>
The goal is indeed to always round closest, so I will add the divider
flags (all of the three divs need it, not just this one).
I based most of those clocks from the ones in GXBB, which do not
include the flags. I'll push a fix for this platform as well.
Cheers,
Maxime
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_names = (const char *[]){ "vdec_1_sel" },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = HHI_VDEC_CLK_CNTL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_names = (const char *[]){ "vdec_1_div" },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_hevcf_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = HHI_VDEC2_CLK_CNTL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_hevcf_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_names = g12a_vdec_parent_names,
> > + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_hevcf_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_VDEC2_CLK_CNTL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_hevcf_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_names = (const char *[]){ "vdec_hevcf_sel" },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_hevcf = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = HHI_VDEC2_CLK_CNTL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_hevcf",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_names = (const char *[]){ "vdec_hevcf_div" },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_hevc_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = HHI_VDEC2_CLK_CNTL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_hevc_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_names = g12a_vdec_parent_names,
> > + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_hevc_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_VDEC2_CLK_CNTL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_hevc_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_names = (const char *[]){ "vdec_hevc_sel" },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap g12a_vdec_hevc = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = HHI_VDEC2_CLK_CNTL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_hevc",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_names = (const char *[]){ "vdec_hevc_div" },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > /* VAPB Clock */
> >
> > static const char * const g12a_vapb_parent_names[] = {
> > @@ -2615,6 +2757,15 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
> > [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
> > [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
> > [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
> > + [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
> > + [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
> > + [CLKID_VDEC_1] = &g12a_vdec_1.hw,
> > + [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
> > + [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
> > + [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
> > + [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
> > + [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
> > + [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
> > [NR_CLKS] = NULL,
> > },
> > .num = NR_CLKS,
> > @@ -2803,6 +2954,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
> > &g12a_cpu_clk_trace,
> > &g12a_pcie_pll_od,
> > &g12a_pcie_pll_dco,
> > + &g12a_vdec_1_sel,
> > + &g12a_vdec_1_div,
> > + &g12a_vdec_1,
> > + &g12a_vdec_hevc_sel,
> > + &g12a_vdec_hevc_div,
> > + &g12a_vdec_hevc,
> > + &g12a_vdec_hevcf_sel,
> > + &g12a_vdec_hevcf_div,
> > + &g12a_vdec_hevcf,
> > };
> >
> > static const struct meson_eeclkc_data g12a_clkc_data = {
> > diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
> > index 1393a09730a6..39c41af70804 100644
> > --- a/drivers/clk/meson/g12a.h
> > +++ b/drivers/clk/meson/g12a.h
> > @@ -189,8 +189,14 @@
> > #define CLKID_PCIE_PLL_DCO 198
> > #define CLKID_PCIE_PLL_DCO_DIV2 199
> > #define CLKID_PCIE_PLL_OD 200
> > +#define CLKID_VDEC_1_SEL 202
> > +#define CLKID_VDEC_1_DIV 203
> > +#define CLKID_VDEC_HEVC_SEL 205
> > +#define CLKID_VDEC_HEVC_DIV 206
> > +#define CLKID_VDEC_HEVCF_SEL 208
> > +#define CLKID_VDEC_HEVCF_DIV 209
> >
> > -#define NR_CLKS 202
> > +#define NR_CLKS 211
> >
> > /* include the CLKIDs that have been made part of the DT binding */
> > #include <dt-bindings/clock/g12a-clkc.h>
>
>
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