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Date:   Fri, 22 Mar 2019 10:11:04 +0800
From:   Shawn Guo <shawnguo@...nel.org>
To:     "Angus Ainslie (Purism)" <angus@...ea.ca>
Cc:     Fabio Estevam <festevam@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        NXP Linux Team <linux-imx@....com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Carlo Caione <ccaione@...libre.com>,
        Abel Vesa <abel.vesa@....com>,
        Daniel Baluta <daniel.baluta@....com>,
        Guido G√ľnther <agx@...xcpu.org>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4] arm64: dts: fsl: imx8mq: enable the multi sensor TMU

On Thu, Mar 21, 2019 at 05:52:52AM -0700, Angus Ainslie (Purism) wrote:
> Add the imx8mq TMU (Thermal management unit) nodes for CPU,
> GPU, and VPU.
> 
> Signed-off-by: Angus Ainslie (Purism) <angus@...ea.ca>

Subject prefix 'arm64: dts: imx8mq:' would be good enough.  I changed it
and applied patch.

Shawn

> ---
> 
> Changes since v3:
> 
> Moved the annotation.
> 
> Changes since v2:
> 
> Updated alert and critical temps for commercial parts.
> Fixed node names.
> 
> Changes since v1:
> 
> Removed references to multi sensor patch.
> 
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
>  1 file changed, 118 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index b39c6c75c043..81d5ce1b1ec1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/power/imx8mq-power.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
>  #include "imx8mq-pinfunc.h"
>  
>  / {
> @@ -89,6 +90,7 @@
>  			reg = <0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&A53_L2>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_1: cpu@1 {
> @@ -97,6 +99,7 @@
>  			reg = <0x1>;
>  			enable-method = "psci";
>  			next-level-cache = <&A53_L2>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_2: cpu@2 {
> @@ -105,6 +108,7 @@
>  			reg = <0x2>;
>  			enable-method = "psci";
>  			next-level-cache = <&A53_L2>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_3: cpu@3 {
> @@ -113,6 +117,7 @@
>  			reg = <0x3>;
>  			enable-method = "psci";
>  			next-level-cache = <&A53_L2>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_L2: l2-cache0 {
> @@ -210,6 +215,119 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> +			tmu: tmu@...60000 {
> +				compatible = "fsl,imx8mq-tmu";
> +				reg = <0x30260000 0x10000>;
> +				interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +				little-endian;
> +				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
> +				fsl,tmu-calibration = <0x00000000 0x00000023
> +						       0x00000001 0x00000029
> +						       0x00000002 0x0000002f
> +						       0x00000003 0x00000035
> +						       0x00000004 0x0000003d
> +						       0x00000005 0x00000043
> +						       0x00000006 0x0000004b
> +						       0x00000007 0x00000051
> +						       0x00000008 0x00000057
> +						       0x00000009 0x0000005f
> +						       0x0000000a 0x00000067
> +						       0x0000000b 0x0000006f
> +
> +						       0x00010000 0x0000001b
> +						       0x00010001 0x00000023
> +						       0x00010002 0x0000002b
> +						       0x00010003 0x00000033
> +						       0x00010004 0x0000003b
> +						       0x00010005 0x00000043
> +						       0x00010006 0x0000004b
> +						       0x00010007 0x00000055
> +						       0x00010008 0x0000005d
> +						       0x00010009 0x00000067
> +						       0x0001000a 0x00000070
> +
> +						       0x00020000 0x00000017
> +						       0x00020001 0x00000023
> +						       0x00020002 0x0000002d
> +						       0x00020003 0x00000037
> +						       0x00020004 0x00000041
> +						       0x00020005 0x0000004b
> +						       0x00020006 0x00000057
> +						       0x00020007 0x00000063
> +						       0x00020008 0x0000006f
> +
> +						       0x00030000 0x00000015
> +						       0x00030001 0x00000021
> +						       0x00030002 0x0000002d
> +						       0x00030003 0x00000039
> +						       0x00030004 0x00000045
> +						       0x00030005 0x00000053
> +						       0x00030006 0x0000005f
> +						       0x00030007 0x00000071>;
> +				#thermal-sensor-cells =  <1>;
> +			};
> +
> +			thermal-zones {
> +				cpu-thermal {
> +					polling-delay-passive = <250>;
> +					polling-delay = <2000>;
> +					thermal-sensors = <&tmu 0>;
> +
> +					trips {
> +						cpu_alert: cpu-alert {
> +							temperature = <80000>;
> +							hysteresis = <2000>;
> +							type = "passive";
> +						};
> +
> +						cpu-crit {
> +							temperature = <90000>;
> +							hysteresis = <2000>;
> +							type = "critical";
> +						};
> +					};
> +
> +					cooling-maps {
> +						map0 {
> +							trip = <&cpu_alert>;
> +							cooling-device =
> +								<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +								<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +								<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +								<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +						};
> +					};
> +				};
> +
> +				gpu-thermal {
> +					polling-delay-passive = <250>;
> +					polling-delay = <2000>;
> +					thermal-sensors = <&tmu 1>;
> +
> +					trips {
> +						gpu-crit {
> +							temperature = <90000>;
> +							hysteresis = <2000>;
> +							type = "critical";
> +						};
> +					};
> +				};
> +
> +				vpu-thermal {
> +					polling-delay-passive = <250>;
> +					polling-delay = <2000>;
> +					thermal-sensors = <&tmu 2>;
> +
> +					trips {
> +						vpu-crit {
> +							temperature = <90000>;
> +							hysteresis = <2000>;
> +							type = "critical";
> +						};
> +					};
> +				};
> +			};
> +
>  			wdog1: watchdog@...80000 {
>  				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
>  				reg = <0x30280000 0x10000>;
> -- 
> 2.17.1
> 

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