linux-kernel - Re: [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller

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Date:   Sun, 24 Mar 2019 17:16:17 -0700 (PDT)
From:   Paul Walmsley <paul.walmsley@...ive.com>
To:     Borislav Petkov <bp@...en8.de>
cc:     Yash Shah <yash.shah@...ive.com>, linux-riscv@...ts.infradead.org,
        linux-edac@...r.kernel.org, palmer@...ive.com,
        paul.walmsley@...ive.com, linux-kernel@...r.kernel.org,
        robh+dt@...nel.org, mark.rutland@....com, aou@...s.berkeley.edu,
        mchehab@...nel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache
 Controller

On Tue, 12 Mar 2019, Borislav Petkov wrote:

> Please no EDAC drivers for a single functional unit with RAS
> capabilities. Rather, a sifive_edac or riscv_edac driver which covers
> the whole platform or even architecture and contains support for all the
> RAS functionality there. See altera_edac, for example.

Looking at the Synopsys, Highbank, PowerPC 4xx, and TI EDAC drivers, all 
of those are clearly for IP block error management, rather than platform 
error management.  Has the upstream guidance changed since those drivers 
were merged?

The core issue for us is that we don't have a generalized "ECC management" 
IP block.  And I would just as soon not fake one in the DT data, since the 
general DT guidance is that the data in DT is meant to describe the actual 
hardware.

Would it make more sense to put this driver outside of drivers/edac?

 - Paul